From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f201.google.com (mail-pl1-f201.google.com [209.85.214.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B9F251FC7 for ; Thu, 21 May 2026 21:17:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779398248; cv=none; b=sP4u+UAhJPOPP9UhZoEWnQLCD01vIcZP+NKFoQNHWcjo3/ss7o3WoZMgg4Hu30bcis88lunWdiscUUKBkit44Voc4L93bcDDsc9Q9a/JoTy8XZJJQwAa6hZNBPf8U520So9yZFd86mdHQFm8jXzkCcGR6OerKYsROJsk+EyAxo0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779398248; c=relaxed/simple; bh=XW2WAcTP4Sm+wf3twJ/QoA4Nko2nJVwNKYlSfZwWKSk=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=hxt3Eo0RkT04HEWp+cbGvyd00xBh7oQ4fNEPTrq8/pIptU2vrlwpN3hIjCfkwyar/C3if6sX5xnFx8yNtn7h/hO4Mcoh19nsRQ8xQ7Bx2ASym7wJuwpnzriW8jQBmapwYPb4PFLrhTCgW2WHaZ0zJ7N8UmqVdPkBjgzy7J1EsgM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=INe6ga14; arc=none smtp.client-ip=209.85.214.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="INe6ga14" Received: by mail-pl1-f201.google.com with SMTP id d9443c01a7336-2b4530a90fdso117127505ad.1 for ; Thu, 21 May 2026 14:17:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20251104; t=1779398246; x=1780003046; darn=vger.kernel.org; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:from:to:cc:subject:date:message-id :reply-to; bh=/jW9XtyrtynBxdJYPv96DfQ4Rw5zedPSv+/BbmcgSxI=; b=INe6ga14hO+LrZApp+y9FDGLXUp87rFwRyJJBIl+Z89cq0GN8oo0/Jg+D/hGu1Acoj QZ3L+uvWmPdBRcM00eL+GbwfszHyGIf77ququvAEP78jtvxrcuiYVA0wy1ToEhlk7W17 xLdK8/BRxRernNhpMaJzEzSpKGQttOvsGyaGt1X2pK5O7xx0KOAKqi474YXK2RWM3M9C sAD4bAginlDYBIx6/uYqXNWnx3Tg80wEPpiyHSZtBIsCK7ydi70Kxcyjlj1iqGZCG4ZC dL7tc53D/fVwPAC/DP2FjEeHv2i0QcGh5A1oI4UoiIlhLuvvI0yXiE5Gt60YwiDLJ5h4 enlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779398246; x=1780003046; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:x-gm-message-state:from:to:cc:subject :date:message-id:reply-to; bh=/jW9XtyrtynBxdJYPv96DfQ4Rw5zedPSv+/BbmcgSxI=; b=rd+K661YMbJREvsiQiU/OVEi3Sh+QhJF046pzlpuNrS7iPJAkLlmqgJ+uWMbWSxTwH o29AO50rx8aWYFUD4rtVqH6dbB5GRa3xyZ+qwVgjvxL9kzbNkt/g9dpAPU/Q1i7G5s02 NsriO2j6h6xOHrbDu1Y4dtGJD3uUFWzDVa6pcxxmNmodx6Nb43yEaqbUnqhutMxs64i9 cAVmcGAVrhQwd6Rmq9hSuDLE/vdhkVx++LVTXY0cA8RcqkQPA8J/nIvuF23d1RBCVzuc W3e5nl5GIO9jt9nrqZ11hwdpEQDxJHLwusFF3Pun93SaHB8/uv6giwnsrBAx9icJ0g2v WGBg== X-Forwarded-Encrypted: i=1; AFNElJ9Qgtj4G5ik9Ax+raGoP9ScQr0QyLq8/QNH+JvJMAfkcuCXWgGKInDD49Yiw3kjfmvAObU=@vger.kernel.org X-Gm-Message-State: AOJu0YxXfQ4znOXSu1cY3LsGzFOVMYthP8IjYi4E+JeWEAl4E5iG308R e/DPoOz4rbz6vMy9vmrW/6JTEsZGdvUiKGBUhBsdY5iwTeiuzR/2ptLDFf9OH2OHTSqHl8klvoB BL9hNzA== X-Received: from plbkh13.prod.google.com ([2002:a17:903:64d:b0:2b0:c78a:4537]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:902:ccd0:b0:2b4:5f19:1d34 with SMTP id d9443c01a7336-2beb05eec0amr6266755ad.17.1779398245853; Thu, 21 May 2026 14:17:25 -0700 (PDT) Date: Thu, 21 May 2026 14:17:25 -0700 In-Reply-To: <342098f6bfe1e4c7b233433df8f79713b4220614.camel@infradead.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260515191942.1892718-1-seanjc@google.com> <20260515191942.1892718-3-seanjc@google.com> <44e0d60548d317fd59895f18bd17220dfb2f834b.camel@infradead.org> <342098f6bfe1e4c7b233433df8f79713b4220614.camel@infradead.org> Message-ID: Subject: Re: [PATCH v3 02/41] x86/tsc: Add helper to register CPU and TSC freq calibration routines From: Sean Christopherson To: David Woodhouse Cc: Kiryl Shutsemau , Paolo Bonzini , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Long Li , Ajay Kaher , Alexey Makhalov , Jan Kiszka , Dave Hansen , Andy Lutomirski , Peter Zijlstra , Juergen Gross , Daniel Lezcano , Thomas Gleixner , John Stultz , Rick Edgecombe , Vitaly Kuznetsov , Broadcom internal kernel review list , Boris Ostrovsky , Stephen Boyd , x86@kernel.org, linux-coco@lists.linux.dev, kvm@vger.kernel.org, linux-hyperv@vger.kernel.org, virtualization@lists.linux.dev, linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org, Michael Kelley , Tom Lendacky , Nikunj A Dadhania , Thomas Gleixner Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Thu, May 21, 2026, David Woodhouse wrote: > On Thu, 2026-05-21 at 13:53 -0700, Sean Christopherson wrote: > >=20 > > E.g. this is what I've got for the early flow.=C2=A0 Testing now.=20 > >=20 > > =C2=A0 void __init tsc_early_init(void) > > =C2=A0 { > > unsigned int known_cpu_khz =3D 0, known_tsc_khz =3D 0; > >=20 > > if (!boot_cpu_has(X86_FEATURE_TSC)) > > return; > > /* Don't change UV TSC multi-chassis synchronization */ > > if (is_early_uv_system()) > > return; > >=20 > > if (x86_init.hyper.get_cpu_khz) > > known_cpu_khz =3D x86_init.hyper.get_cpu_khz(); > >=20 > > if (tsc_early_khz) > > known_tsc_khz =3D tsc_early_khz; > > else if (cc_platform_has(CC_ATTR_GUEST_SNP_SECURE_TSC)) > > known_tsc_khz =3D snp_secure_tsc_init(); > > else if (boot_cpu_has(X86_FEATURE_TDX_GUEST)) > > known_tsc_khz =3D tdx_tsc_init(); > >=20 > > /* > > * If the TSC frequency is still unknown, i.e. not provided by the use= r > > * or by trusted firmware, try to get it from the hypervisor (which is > > * untrusted when running as a CoCo guest). > > */ > > if (!known_tsc_khz && x86_init.hyper.get_tsc_khz) > > known_tsc_khz =3D x86_init.hyper.get_tsc_khz(); > >=20 > > if (known_tsc_khz) > > setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ); > >=20 > > if (!determine_cpu_tsc_frequencies(true, known_cpu_khz, known_tsc_khz)= ) > > return; > > tsc_enable_sched_clock(); > > =C2=A0 } >=20 > That seems reasonable. Where does the call to native_calibrate_tsc() > happen; is that from determine_cpu_tsc_frequencies()?=20 Yep. static bool __init determine_cpu_tsc_frequencies(bool early, unsigned int known_cpu_khz, unsigned int known_tsc_khz) { /* Make sure that cpu and tsc are not already calibrated */ WARN_ON(cpu_khz || tsc_khz); if (early) { /* * Early CPU calibration can only use methods that are available * early in boot (obviously). */ if (known_cpu_khz) cpu_khz =3D known_cpu_khz; else cpu_khz =3D native_calibrate_cpu_early(); if (known_tsc_khz) tsc_khz =3D known_tsc_khz; else tsc_khz =3D native_calibrate_tsc(); } else { cpu_khz =3D pit_hpet_ptimer_calibrate_cpu(); } ...