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AFNElJ+v1aoyd+hlBcFWq+jS+rVPu3Oa6SZ0FlEYeJwCfRFZKHwyf+rw7jVP6NLiaouu/CPGz4M=@vger.kernel.org X-Gm-Message-State: AOJu0Yyt66RjiB3GGCCFmaT0WFyLjHJ9f2pgQ+f6pevodIDrTxlbROyL daLDy4khx/IkEsE1+LRLu8QF5JuMJOsVRobf6KJRF9fRa1I5azb4oGBkFmOMGqclGItxIyPD5Wu u5/TiWw== X-Received: from pfua29.prod.google.com ([2002:a05:6a00:11dd:b0:837:a076:d251]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a00:a96:b0:82f:6cb3:645a with SMTP id d2e1a72fcca58-8414b5956bemr21117260b3a.31.1779895224781; Wed, 27 May 2026 08:20:24 -0700 (PDT) Date: Wed, 27 May 2026 08:20:24 -0700 In-Reply-To: Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260526031704.109102-1-chenyi.qiang@intel.com> <20260526031704.109102-3-chenyi.qiang@intel.com> Message-ID: Subject: Re: [kvm-unit-tests PATCH v2 2/4] nVMX: Validate DEBUGCTLMSR_BUS_LOCK_DETECT states during VMX transitions From: Sean Christopherson To: Xiaoyao Li Cc: Chenyi Qiang , kvm@vger.kernel.org, Paolo Bonzini Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Wed, May 27, 2026, Xiaoyao Li wrote: > On 5/27/2026 10:58 PM, Sean Christopherson wrote: > > On Wed, May 27, 2026, Chenyi Qiang wrote: > > > On 5/26/2026 8:32 PM, Xiaoyao Li wrote: > > > > On 5/26/2026 11:16 AM, Chenyi Qiang wrote: > > > > > diff --git a/x86/unittests.cfg b/x86/unittests.cfg > > > > > index 48835eba..c8426770 100644 > > > > > --- a/x86/unittests.cfg > > > > > +++ b/x86/unittests.cfg > > > > > @@ -471,6 +471,14 @@ arch =3D x86_64 > > > > > =C2=A0 groups =3D vmx > > > > > =C2=A0 timeout =3D 240 > > > > > =C2=A0 +[vmx_bus_lock_detect_test] > > > > > +file =3D vmx.flat > > > > > +test_args =3D "vmx_bus_lock_detect_test" > > > > > +qemu_params =3D -cpu max,+vmx > > > > > +arch =3D x86_64 > > > > > +groups =3D vmx > > > > > +timeout =3D 240 > >=20 > > Why does this need a separate config, and with a massive timeout? This= should > > be nearly instantaneous, no? > >=20 > > Ugh, because you copy+pasted vmx_cet. That thing doesn't need to exist= , the > > testcase is run by the common "vmx" entry. I'll send a patch to drop v= mx_cet. >=20 > I told Chenyi that to actually be able to test LBR bit, we might need som= e > specific QEMU configuration to enable PMU and legacy LBR and it will need= a > specific config. Ah. AFAICT, it's just the migratable=3Dno thing? If so, any reason we can= 't do that for the main "vmx" testcase? diff --git x86/unittests.cfg x86/unittests.cfg index 48835eba..fad58255 100644 --- x86/unittests.cfg +++ x86/unittests.cfg @@ -320,7 +320,7 @@ qemu_params =3D -cpu max,host-phys-bits [vmx] file =3D vmx.flat test_args =3D "-exit_monitor_from_l2_test -ept_access* -vmx_smp* -vmx_vmcs= _shadow_test -atomic_switch_overflow_msrs_test -vmx_init_signal_test -vmx_a= pic_passthrough_tpr_threshold_test -apic_reg_virt_test -virt_x2apic_mode_te= st -vmx_pf_exception_test -vmx_pf_exception_forced_emulation_test -vmx_pf_n= o_vpid_test -vmx_pf_invvpid_test -vmx_pf_vpid_test -vmx_basic_vid_test -vmx= _eoi_virt_test -vmx_posted_interrupts_test" -qemu_params =3D -cpu max,+vmx +qemu_params =3D -cpu max,migratable=3Dno,+vmx arch =3D x86_64 groups =3D vmx