Re: [PATCH v7 10/17] KVM: x86/pmu: Disable counters based on Host-Only/Guest-Only bits in SVM

[Sean Christopherson <seanjc@google.com>]

On Thu, May 28, 2026, sashiko-bot@kernel.org wrote:
> > diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c
> > index 7aa298eeb0721..41ee6532290e9 100644
> > --- a/arch/x86/kvm/svm/pmu.c
> > +++ b/arch/x86/kvm/svm/pmu.c
> [ ... ]
> > +static bool amd_pmc_is_disabled_in_current_mode(struct kvm_pmc *pmc)
> > +{
> > +	struct kvm_vcpu *vcpu = pmc->vcpu;
> > +	u64 host_guest_bits;
> > +
> > +	if (!kvm_vcpu_has_mediated_pmu(vcpu))
> > +		return false;
> > +
> > +	/* Common code is supposed to check the common enable bit */
> > +	if (WARN_ON_ONCE(!(pmc->eventsel & ARCH_PERFMON_EVENTSEL_ENABLE)))
> > +		return false;
> > +
> > +	/* If both bits are cleared, the counter is always enabled */
> > +	host_guest_bits = pmc->eventsel & AMD64_EVENTSEL_HOST_GUEST_MASK;
> > +	if (!host_guest_bits)
> > +		return false;
> > +
> > +	/* If EFER.SVME=0 and either bit is set, the counter is disabled */
> > +	if (!(vcpu->arch.efer & EFER_SVME))
> 
> [Severity: High]
> Does this correctly evaluate the L1 guest's EFER.SVME bit, or does it evaluate
> the L2 guest's EFER.SVME bit during nested execution?
> 
> When L1 programs a Guest-Only PMU counter to profile the L2 guest, KVM
> evaluates L1's PMU configuration. However, during nested execution,
> vcpu->arch.efer reflects the L2 guest's EFER.
> 
> Since most L2 guests do not enable nested SVM (meaning L2's EFER.SVME is 0),
> could this cause the counter to be incorrectly disabled, preventing L1 from
> profiling L2?

VMRUN fails if EFER.SVME isn't set in the VMCB save area, i.e. in vmcb12, and
clearing EFER.SVME while in guest mode is architecturally undefined (KVM triple
faults the entire VM).  I.e. this can't happen.