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Peter Anvin" , "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Tue, Jun 02, 2026, Sean Christopherson wrote: > On Mon, Jun 01, 2026, Carlos L=C3=B3pez wrote: > > The practical impact is limited, as check_dr_write() already checks DR6 > > and DR7 manually. However, it misses DR4/DR5, which alias DR6/DR7 when > > CR4.DE=3D0. >=20 > *sigh* (not at your patch, at the existing code) >=20 > Which, after digging into *why* check_dr_write() checks DR6/DR7, highligh= ts that > this fix is incomplete. em_dr_write() can't rely on ->set_dr() for #GP c= hecks, > because unfortunately for us, the #GP check has priority over DR intercep= ts on > SVM, and over DR7.GD (General Detect) #DBs. And testing fail. The DR7.GD #DB has priority, I forgot that DR7.GD is cle= ared by the CPU on delivery of the #DB.