From: Charlie Jenkins <thecharlesjenkins@gmail.com>
To: "Radim Krčmář" <radim.krcmar@oss.qualcomm.com>
Cc: Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Nam Cao <namcao@linutronix.de>, Alexandre Ghiti <alex@ghiti.fr>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atish.patra@linux.dev>,
Conor Dooley <conor@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Andrew Morton <akpm@linux-foundation.org>,
Shuah Khan <shuah@kernel.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-kselftest@vger.kernel.org
Subject: Re: [PATCH v2 01/16] riscv: Introduce instruction table generation
Date: Tue, 30 Jun 2026 18:17:31 -0700 [thread overview]
Message-ID: <akRqqxVMmzCJUpxp@blinky> (raw)
In-Reply-To: <DJMJB4B8Q57Y.34SUOKB6MD8IE@oss.qualcomm.com>
On Tue, Jun 30, 2026 at 06:45:51PM +0200, Radim Krčmář wrote:
> 2026-06-21T21:01:19-07:00, Charlie Jenkins via B4 Relay <devnull+thecharlesjenkins.gmail.com@kernel.org>:
> > From: Charlie Jenkins <thecharlesjenkins@gmail.com>
> >
> > Eliminate the need to hand-write riscv instructions by using a shell
> > script to autogenerate a header from an instruction table. This is modeled
> > after the syscall table infrastructure.
> >
> > The table is generated externally by riscv-unified-db [1], but is
> > in a simple format to make it possible to use other tools or modify
> > manually.
> >
> > [1] https://github.com/riscv-software-src/riscv-unified-db
> >
> > Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com>
> >
> > ---
> > diff --git a/arch/riscv/tools/insn.tbl b/arch/riscv/tools/insn.tbl
> > @@ -0,0 +1,1392 @@
> > +# SPDX-License-Identifier: BSD-3-Clause-Clear
> > +#
> > +# GENERATED WITH https://github.com/riscv-software-src/riscv-unified-db
> > +# "./bin/generate inst-table -o test_table.txt"
>
> I checked out the repo, ran the command, and got a different table:
>
> > +andn common 0100000<25|111<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
> andn common 0100000<31|111<14|0110011<7 xs2=24-20 xs1=19-15 xd=11-7
>
> I assume there were some recent changes in the output format...
>
> I think it would be nice to use their latest format and also note the
> UDB commit that was used, so it's easier to reproduce our file.
> Hopefully there won't be breaking changes too often. :)
I have a PR open to fix this bug that I missed when it got merged, once
that gets merged I can link the hash and there will no longer be this
mismatch.
>
> Thanks.
>
> ---
> Sashiko seems to have noticed a plenty of other issues, so I didn't
> review more...
Oh thanks, I'll check that out.
- Charlie
next prev parent reply other threads:[~2026-07-01 1:17 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-22 4:01 [PATCH v2 00/16] riscv: Generate riscv instruction functions Charlie Jenkins via B4 Relay
2026-06-22 4:01 ` [PATCH v2 01/16] riscv: Introduce instruction table generation Charlie Jenkins via B4 Relay
2026-06-22 4:13 ` sashiko-bot
2026-06-30 16:45 ` Radim Krčmář
2026-07-01 1:17 ` Charlie Jenkins [this message]
2026-06-22 4:01 ` [PATCH v2 02/16] riscv: alternatives: Use generated instruction headers for patching code Charlie Jenkins via B4 Relay
2026-06-22 4:28 ` sashiko-bot
2026-06-29 18:07 ` Jesse Taube
2026-06-22 4:01 ` [PATCH v2 03/16] riscv: kgdb: Use generated instruction headers Charlie Jenkins via B4 Relay
2026-06-22 4:01 ` [PATCH v2 04/16] riscv: Add kprobes instruction simulation KUnit Charlie Jenkins via B4 Relay
2026-06-22 4:19 ` sashiko-bot
2026-06-22 4:01 ` [PATCH v2 05/16] riscv: kprobes: Use generated instruction headers Charlie Jenkins via B4 Relay
2026-06-22 4:01 ` [PATCH v2 06/16] riscv: cfi: " Charlie Jenkins via B4 Relay
2026-06-22 4:35 ` sashiko-bot
2026-06-22 4:01 ` [PATCH v2 07/16] riscv: Use generated instruction headers for misaligned loads/stores Charlie Jenkins via B4 Relay
2026-06-22 4:18 ` sashiko-bot
2026-06-29 20:20 ` Jesse T
2026-06-30 6:14 ` Charlie Jenkins
2026-06-22 4:01 ` [PATCH v2 08/16] riscv: kvm: Use generated instruction headers for csr code Charlie Jenkins via B4 Relay
2026-06-22 4:18 ` sashiko-bot
2026-06-29 20:25 ` Jesse T
2026-06-30 6:17 ` Charlie Jenkins
2026-06-22 4:01 ` [PATCH v2 09/16] KVM: device: Add test device Charlie Jenkins via B4 Relay
2026-06-22 4:13 ` sashiko-bot
2026-06-22 4:01 ` [PATCH v2 10/16] KVM: riscv: selftests: Add mmio test Charlie Jenkins via B4 Relay
2026-06-22 4:18 ` sashiko-bot
2026-06-22 4:01 ` [PATCH v2 11/16] riscv: kvm: Use generated instruction headers for mmio emulation Charlie Jenkins via B4 Relay
2026-06-22 4:27 ` sashiko-bot
2026-06-22 4:01 ` [PATCH v2 12/16] riscv: kvm: Add emulated test csr Charlie Jenkins via B4 Relay
2026-06-22 4:23 ` sashiko-bot
2026-06-22 4:01 ` [PATCH v2 13/16] KVM: riscv: selftests: Add csr emulation test Charlie Jenkins via B4 Relay
2026-06-22 4:24 ` sashiko-bot
2026-06-22 4:01 ` [PATCH v2 14/16] riscv: kvm: Use generated instruction headers for csr emulation Charlie Jenkins via B4 Relay
2026-06-22 4:30 ` sashiko-bot
2026-06-22 4:01 ` [PATCH v2 15/16] riscv: kexec: Use generated instruction headers for kexec relocations Charlie Jenkins via B4 Relay
2026-06-22 4:01 ` [PATCH v2 16/16] riscv: Remove unused instruction headers Charlie Jenkins via B4 Relay
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