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AHgh+RrPlxVnBYnj2vT84B9iRkySn9/u0rTMWVJc8/jbFPqAOZcmuk5vdGfGdPLm+S3llhVxcWg=@vger.kernel.org X-Gm-Message-State: AOJu0Yzd8+8d236+0YlgB6viAeNINOiGWA4hZTgDrfnk5/kHUSluH4tM Cn8V4NT3EG6dk95e+/fxU5yomtGeBcFEVsbPN9uwVrsXpk7N595z6h91vDtzgNjJEy2m48V74wY ukbKExQ== X-Received: from plbbi9.prod.google.com ([2002:a17:902:bf09:b0:2bf:195a:2b9d]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:902:e74b:b0:2c7:fc03:fcf0 with SMTP id d9443c01a7336-2ca91151163mr8962085ad.17.1782917946247; Wed, 01 Jul 2026 07:59:06 -0700 (PDT) Date: Wed, 1 Jul 2026 07:59:05 -0700 In-Reply-To: <20260701110547.764083-3-kirill@shutemov.name> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260701110547.764083-1-kirill@shutemov.name> <20260701110547.764083-3-kirill@shutemov.name> Message-ID: Subject: Re: [PATCH v5 2/3] x86/insn-eval: Add insn_assign_reg() helper From: Sean Christopherson To: Kiryl Shutsemau Cc: Dave Hansen , Thomas Gleixner , Ingo Molnar , Borislav Petkov , x86@kernel.org, Paolo Bonzini , Kuppuswamy Sathyanarayanan , Kai Huang , Xiaoyao Li , Rick Edgecombe , Binbin Wu , David Laight , Andi Kleen , Dan Williams , Borys Tsyrulnikov , kvm@vger.kernel.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, stable@vger.kernel.org, "Kiryl Shutsemau (Meta)" Content-Type: text/plain; charset="us-ascii" On Wed, Jul 01, 2026, Kiryl Shutsemau wrote: > From: "Kiryl Shutsemau (Meta)" > > KVM's instruction emulator has a small helper, assign_register(), that > writes a value into a sub-register with x86 partial-register-write > semantics: 1- and 2-byte writes leave the upper bits of the destination > untouched, 4-byte writes zero-extend to 64 bits, 8-byte writes overwrite > the full register. > > The TDX guest #VE handler needs the same logic for port I/O emulation > to get 32-bit zero-extension right. Rather than copy-pasting the > helper, lift it to as insn_assign_reg() so both can > use it. > > Add to the header's includes so it builds standalone in > callers that have not pulled it in transitively. > > No functional change. > > Signed-off-by: Kiryl Shutsemau (Meta) > Cc: stable@vger.kernel.org # prerequisite for the following 32-bit port I/O zero-extension fix > --- > arch/x86/include/asm/insn-eval.h | 30 ++++++++++++++++++++++++++++++ > arch/x86/kvm/emulate.c | 26 ++++---------------------- > 2 files changed, 34 insertions(+), 22 deletions(-) > > diff --git a/arch/x86/include/asm/insn-eval.h b/arch/x86/include/asm/insn-eval.h > index 4733e9064ee5..0c87759816d3 100644 > --- a/arch/x86/include/asm/insn-eval.h > +++ b/arch/x86/include/asm/insn-eval.h > @@ -9,6 +9,7 @@ > #include > #include > #include > +#include > #include > > #define INSN_CODE_SEG_ADDR_SZ(params) ((params >> 4) & 0xf) > @@ -46,4 +47,33 @@ enum insn_mmio_type insn_decode_mmio(struct insn *insn, int *bytes); > > bool insn_is_nop(struct insn *insn); > > +/* > + * Write @val into *@reg with x86 partial-register-write semantics: a 1- > + * or 2-byte write leaves the upper bits of the destination untouched; a > + * 4-byte write zero-extends to 64 bits (matching IN[BWL], MOV[BWL] The placement of the "(matching IN[BWL], MOV[BWL] etc.)" blurb is confusing. I *think* you're trying to say this behavior matches that of MOVB, MOVW, and MOVL instruction mnemonics, but the blurb is buried in the snippet that specifically describes the 4-byte write behavior. FWIW, I think giving examples does more harm than good, because the behavior isn't instruction specific, it's architectural behavior that applies to all writes to GPRs, as defined in "3.4.1.1 General-Purpose Registers in 64-Bit Mode". E.g. for a MOV instruction that sign-extends a 32-bit immediate to a 64-bit registers, it's not that the instruction is exempt from the normal GPR semenatics, it's that the instruction performs a 64-bit write to the destination even though the source is only 32 bits. And the B/W/L terminology isn't architectural, it's AT&T syntax. E.g. trying to encode "movl" with NASM yields "error: instruction expected, found `movl dword'". Yes, the kernel uses AT&T syntax for assembly, but I think this helper should very explicitly document that it's emulating architectural behavior. > + * etc.); an 8-byte write overwrites the full register. > + * > + * @reg need not be 8-byte aligned: KVM's instruction emulator points > + * into the middle of a register slot to address the high-byte > + * registers (AH, CH, DH, BH). Use narrow stores for the sub-word > + * cases so that the access width matches @bytes. > + */ > +static inline void insn_assign_reg(unsigned long *reg, u64 val, int bytes) > +{ > + switch (bytes) { > + case 1: > + *(u8 *)reg = (u8)val; > + break; > + case 2: > + *(u16 *)reg = (u16)val; > + break; > + case 4: > + *reg = (u32)val; IMO, it's worth keeping a short comment here, because even with the explanation above, I suspect most people will think the code is buggy. E.g. /* As above, zero-extend 4-byte writes on 64-bit CPUs. */ *reg = (u32)val; > + break; > + case 8: > + *reg = val; > + break; > + } > +}