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AHgh+RrZ3c6HsAvfrGyWRsFRg8tlHJfKnO38YBb8S7VyAZ7CA8HG0DRPm5dXcW3udlLZAir+0L8=@vger.kernel.org X-Gm-Message-State: AOJu0Yxvr6xCs2z9EOyWUkhfZSOy0FZR/pefM+sUnOMstDYKixf8Q2h1 Fp2g8mIK80SjEPCYz8frJRnl3O7cBy0O7aaoSdaCwu64RYYtITKW8TXOk6+NgpJi0iEV0jO9cMW sPGVs5g== X-Received: from plq4.prod.google.com ([2002:a17:903:2f84:b0:2cc:73ae:7d4c]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:902:cec4:b0:2ca:ca48:c380 with SMTP id d9443c01a7336-2ccbf1ace49mr32602895ad.47.1783394487964; Mon, 06 Jul 2026 20:21:27 -0700 (PDT) Date: Mon, 6 Jul 2026 20:21:27 -0700 In-Reply-To: Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260629125205.52394-1-zhang_wei@open-hieco.net> <0e576fd8d8cd2ed1739cee36eba393fea7745506.camel@redhat.com> Message-ID: Subject: Re: [PATCH 0/2] KVM: nSVM: Expose DecodeAssists to L1 From: Sean Christopherson To: Tina Zhang Cc: Jim Mattson , mlevitsk@redhat.com, Paolo Bonzini , kvm@vger.kernel.org, Shuah Khan , zhouyanjing@hygon.cn, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Tue, Jul 07, 2026, Tina Zhang wrote: >=20 >=20 > On 7/7/2026 9:32 AM, Jim Mattson wrote: > > On Mon, Jul 6, 2026 at 5:02=E2=80=AFPM Tina Zhang wrote: > >=20 > > > I will take another look for the next version and try to handle the > > > remaining pieces properly, while also making sure we don't expose sta= le > > > or incorrectly synthesized decode-assist state for emulated exits. > >=20 > > Naples erratum 1096 seems to imply that the instruction bytes stored > > in the VMCB are not necessarily the same instruction bytes that were > > fetched and decoded to lead to the #PF/#NPF. Hence, in the case of > > emulation, it might be sufficient to read the instruction bytes quite > > late in nested_svm_vmexit(). That would certainly simplify the > > plumbing. The plumbing doesn't seem all that complex though. > Thanks for the suggestion, and for pointing me at Naples erratum 1096. I > wasn't aware of that erratum. >=20 > My understanding is that late fetching/decoding from guest RIP is not > strictly equivalent to preserving the exact bytes observed by the origina= l > decoder, as the code bytes or translations could theoretically change in > between. But the suggested workaround for erratum 1096 also tells the > hypervisor to decode the instruction at the instruction pointer when > GuestInstrBytes cannot be used, so it seems that this is an acceptable > model/fallback. >=20 > For KVM-synthesized/emulated #PF/#NPF nested VM-Exits there is no fresh > hardware GuestInstrBytes state to propagate to VMCB12. So I agree that it > should be simpler to avoid plumbing instruction bytes from the emulator, = and > instead fetch the bytes late when constructing the nested VM-Exit for L1. >=20 > I'll try this direction first. I'd rather not, at least not as the primary way. It's going to raise a dif= ferent set of issues, e.g. how to behave if reading guest memory fails. That's pr= obably unavoidable, e.g. if reading the INVPCID descriptor fails, then KVM doesn't= even have a pre-decoded instruction to work with, but it should ideally be a las= t resort. E.g. where the NULL case triggers an on-demand read of guest memory. diff --git arch/x86/kvm/svm/nested.c arch/x86/kvm/svm/nested.c index ba985a02208a..812af3a8d8b9 100644 --- arch/x86/kvm/svm/nested.c +++ arch/x86/kvm/svm/nested.c @@ -42,6 +42,7 @@ static void nested_svm_inject_npf_exit(struct kvm_vcpu *v= cpu, struct vcpu_svm *svm =3D to_svm(vcpu); struct vmcb *vmcb =3D svm->vmcb; u64 fault_stage; + u8 *insn_bytes; =20 /* * For hardware NPF exits, the GUEST_FAULT_STAGE bits are only @@ -68,7 +69,14 @@ static void nested_svm_inject_npf_exit(struct kvm_vcpu *= vcpu, (fault->error_code & ~PFERR_GUEST_FAULT= _STAGE_MASK); vmcb->control.exit_info_2 =3D fault->address; =20 - nested_svm_vmexit(svm); + if (from_hardware) + insn_bytes =3D svm->nested.vmcb02.ptr->control.insn_bytes; + else if (vcpu->arch.emulate_ctxt->eip =3D=3D kvm_rip_read(vcpu)) + insn_bytes =3D vcpu->arch.emulate_ctxt->fetch.data + else + insn_bytes =3D NULL; + + nested_svm_vmexit(svm, insn_bytes); } =20 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)