From mboxrd@z Thu Jan  1 00:00:00 1970
From: "Maciej W. Rozycki" <macro@linux-mips.org>
Subject: Re: [PATCH 00/18] KVM/MIPS32: Support for the new Virtualization
 ASE (VZ-ASE)
Date: Mon, 27 May 2013 13:45:11 +0100 (BST)
Message-ID: <alpine.LFD.2.03.1305202029460.10753@linux-mips.org>
References: <n> <1368942460-15577-1-git-send-email-sanjayl@kymasys.com> <519A4640.6060202@gmail.com> <456B70C6-A896-4B94-B8EF-DE6ED26CE859@kymasys.com> <alpine.LFD.2.03.1305201930570.10753@linux-mips.org> <519A7249.1030302@gmail.com>
Mime-Version: 1.0
Content-Type: TEXT/PLAIN; charset=US-ASCII
Cc: Sanjay Lal <sanjayl@kymasys.com>, kvm@vger.kernel.org,
	linux-mips@linux-mips.org, Ralf Baechle <ralf@linux-mips.org>,
	Gleb Natapov <gleb@redhat.com>,
	Marcelo Tosatti <mtosatti@redhat.com>
To: David Daney <ddaney.cavm@gmail.com>
Return-path: <kvm-owner@vger.kernel.org>
Received: from eddie.linux-mips.org ([78.24.191.182]:55349 "EHLO
	cvs.linux-mips.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
	with ESMTP id S932477Ab3E0MpM (ORCPT <rfc822;kvm@vger.kernel.org>);
	Mon, 27 May 2013 08:45:12 -0400
Received: from localhost.localdomain ([127.0.0.1]:50296 "EHLO
        localhost.localdomain" rhost-flags-OK-OK-OK-OK)
        by eddie.linux-mips.org with ESMTP id S6823763Ab3E0MpL0Rvfe (ORCPT
        <rfc822;kvm@vger.kernel.org>); Mon, 27 May 2013 14:45:11 +0200
In-Reply-To: <519A7249.1030302@gmail.com>
Sender: kvm-owner@vger.kernel.org
List-ID: <kvm.vger.kernel.org>

On Mon, 20 May 2013, David Daney wrote:

> >   That's rather risky as the implementation of this register (and its
> > presence in the first place) is processor-specific.  Do you maintain a
> > list of PRId values the use of this register is safe with?
> > 
> 
> FWIW:  The MIPS-VZ architecture module requires the presence of CP0 scratch
> registers that can be used for this in the exception handlers without having
> to worry about using these implementation dependent registers.  For the
> trap-and-emulate only version, there really is no choice other than to
> re-purpose some of the existing CP0 registers.

 Sure, I've just been wondering what the implementation does to make sure 
it does not go astray on a random processor out there.

 FWIW, offhand the ErrorEPC register, that's been universally present 
since MIPS III (and I doubt anyone cares of virtualising on earlier 
implementations), seems to me promising as a better choice -- of course 
that register can get clobbered if an error-class exception happens early 
on in exception processing, but in that case we're in a worse trouble than 
just clobbering one of the guest registers anyway and likely cannot 
recover at all regardless.

  Maciej