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Tsirkin" , Paolo Bonzini , Marcelo Tosatti Subject: Re: [PATCH v1 8/9] target/i386: Use AMD legacy cache fallback for Hygon Message-ID: References: <20260706055530.1752094-1-zhang_wei@open-hieco.net> <20260706055530.1752094-9-zhang_wei@open-hieco.net> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260706055530.1752094-9-zhang_wei@open-hieco.net> On Mon, Jul 06, 2026 at 01:55:29PM +0800, zhang_wei@open-hieco.net wrote: > Date: Mon, 6 Jul 2026 13:55:29 +0800 > From: zhang_wei@open-hieco.net > Subject: [PATCH v1 8/9] target/i386: Use AMD legacy cache fallback for Hygon > X-Mailer: git-send-email 2.43.7 > > From: Tina Zhang > > When legacy-cache=on, x86_cpu_realizefn() builds a hardcoded cache > model. It selected the AMD legacy cache table only for CPUs with the > AuthenticAMD vendor ID. Dhyana uses the HygonGenuine vendor ID, so this > explicit compatibility path fell back to QEMU's old Intel legacy cache > table. > > The wrong table is visible through AMD extended cache leaves. With the > Intel legacy table, Dhyana reports 32 KiB, 8-way L1 caches in CPUID > 0x80000005 and a 4 MiB, 16-way L2 cache in CPUID 0x80000006. Linux > uses the AMD/Hygon cache enumeration path for Hygon and reads these AMD > extended cache leaves. > > Use the AMD legacy cache table for Hygon in this fallback path when the > new Hygon vendor ABI fixes are enabled. > Keep the old fallback for pc-11.0 and > older machine types through x-hygon-vendor-abi-fixes=false. > > The default Dhyana model is unchanged because it provides EPYC cache_info > and therefore defaults legacy-cache to off. The guest-visible change is > limited to users who explicitly configure legacy-cache=on on new machine > types. > > Signed-off-by: Tina Zhang > --- > target/i386/cpu.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Zhao Liu