Re: [PATCH 1/5] target/i386: Add support for LASS in CPUID enumeration

[Zhao Liu <zhao1.liu@intel.com>]

On Tue, Aug 25, 2026 at 08:57:30PM -0700, Kishen Maloor wrote:
> Date: Tue, 25 Aug 2026 20:57:30 -0700
> From: Kishen Maloor <kishen.maloor@intel.com>
> Subject: [PATCH 1/5] target/i386: Add support for LASS in CPUID enumeration
> X-Mailer: git-send-email 2.47.1
> 
> From: Isaku Yamahata <isaku.yamahata@intel.com>
> 
> Linear Address Space Separation (LASS) is a security feature that
> prevents a class of side-channel attacks relying on speculative
> accesses across the user/kernel boundary. Paging, along with SMEP
> and SMAP, already provides mode-based access protection, but
> enforcing it requires a page walk whose timing can leak the
> layout of kernel memory.
> 
> LASS applies the equivalent protections during linear-address
> pre-processing, before any page walk. Given the usual partitioning of
> the linear address space into a user half (bit 63 clear) and a
> supervisor half (bit 63 set), an access targeting the opposite half is
> rejected on the basis of bit 63 alone, raising a #GP. LASS is enabled
> via CR4.LASS[bit 27] and applies only in IA-32e mode.
> 
> Feature bit:
>   CPUID.(EAX=7,ECX=1):EAX[6]
> 
> A CPUID_7_1_EAX_LASS macro was previously added in commit 31df29c532a9
> ("i386/tdx: Add supported CPUID bits related to TD Attributes"), but the
> bit was left unnamed in feature_word_info[FEAT_7_1_EAX]. Add the "lass"
> feature name to expose it via -cpu host, -cpu max, or an explicit +lass.
> 
> Exposing LASS to a guest also requires KVM support: KVM must validate
> the CPUID bit and CR4.LASS, and enforce LASS violations in its
> instruction emulator.
> 
> LASS is not implemented in TCG, so the bit is not added to
> TCG_7_1_EAX_FEATURES.
> 
> More details can be found in the Intel 64 and IA-32 Architectures
> Software Developer's Manual, Volume 3A, Section 4.3,
> "Linear-Address-Space Separation (LASS)".
> 
> Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com>
> [kishen: rewrote commit message, rebased]
> Signed-off-by: Kishen Maloor <kishen.maloor@intel.com>
> ---
> KVM support for LASS is currently under review:
> https://lore.kernel.org/kvm/20260806011536.4172258-1-sohil.mehta@intel.com/
> 
>  target/i386/cpu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>