From: Sean Christopherson <seanjc@google.com>
To: Sandipan Das <sandipan.das@amd.com>
Cc: kvm@vger.kernel.org, Paolo Bonzini <pbonzini@redhat.com>,
Dapeng Mi <dapeng1.mi@linux.intel.com>,
Zide Chen <zide.chen@intel.com>,
"Nikunj A . Dadhania" <nikunj@amd.com>,
Manali Shukla <manali.shukla@amd.com>
Subject: Re: [kvm-unit-tests PATCH] x86/pmu: Add option to raise NMI on overflow
Date: Wed, 30 Sep 2026 14:07:24 -0700 [thread overview]
Message-ID: <ar16DP3mAeWTewq8@google.com> (raw)
In-Reply-To: <106bc3a4660653cb7750f3ae07a4dbca42c2762c.1786356229.git.sandipan.das@amd.com>
On Mon, Aug 10, 2026, Sandipan Das wrote:
> Interrupts raised on counter overflow are currently delivered through
> the PMI_VECTOR as regular maskable interrupts. However, for some
> configurations, like SVM with PMC virtualization and VNMI enabled, the
> guest LVTPC is ignored and the interrupts are always delivered as NMIs.
IMO, that's a KVM bug. KVM shouldn't enable PMC virtualization if the guest LVTPC
is configured for something other than NMI.
> This causes the test to crash, as seen below, because it does not
> expect NMIs.
>
> Unhandled exception 2 #NMI(0) at ip 0000000000400326
> error_code=0000 rflags=00000056 cs=00000008
> rax=00000000001300c0 rcx=00000000c0010202 rdx=0000000000000000 rbx=0000000001019f58
> rbp=0000000001019ee0 rsi=00000000000f4240 rdi=0000000001019f58
> r8=ffffffffffffe000 r9=00000000000003f8 r10=000000000000000d r11=0000000000000020
> r12=00000000001300c0 r13=ffffffffff6768f0 r14=ffffffffff6768f0 r15=0000000000000001
> cr0=0000000080010011 cr2=0000000000000000 cr3=00000000010fe000 cr4=0000000000000020
> cr8=0000000000000000
> STACK: @400326 400de1 401715 401e51 4001bd
>
> Add an optional "nmi" argument to improve test coverage for such
> configurations. When passed, the LVTPC has the delivery mode changed to
> NMI (APIC_DM_NMI) and the overflow handler is installed on the
> NMI_VECTOR. Otherwise, it keeps using the maskable PMI_VECTOR.
>
> Unlike maskable interrupts, which stay pending until EFLAGS.IF is set,
> an NMI is not gated by it and arrives as soon as the counter overflows.
Hmm, AMD does have GIF though. What if we conditioned use of NMI on (nested) SVM
support and thus STGI+CLGI being available? Then we can largely abstract away
interrupt masking, and if we wanted, we could even do that in advance of NMI
support since GIF=0 should block IRQs as well.
prev parent reply other threads:[~2026-09-30 21:07 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-10 10:10 [kvm-unit-tests PATCH] x86/pmu: Add option to raise NMI on overflow Sandipan Das
2026-09-30 21:07 ` Sean Christopherson [this message]
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