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[2a02:3100:a9cc:4401:9c3:9199:30c4:c6a3]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e3ebc3cfasm12003158f8f.17.2026.10.25.13.30.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Oct 2026 13:30:31 -0700 (PDT) Date: Sun, 25 Oct 2026 21:30:29 +0100 From: Karl Mehltretter To: Oliver Upton Cc: Marc Zyngier , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Mark Rutland , Eric Auger , Paolo Bonzini , Sean Christopherson , Shuah Khan , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH 0/3] KVM: arm64: Preserve level IRQ re-pending Message-ID: References: <20261022064628.4206-1-kmehltretter@gmail.com> X-Mailing-List: kvm@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Fri, Oct 23, 2026 at 11:55:57PM +0100, Oliver Upton wrote: > > The exact alternative is to stop and synchronize the target vCPU > > before applying such a write, as the active-state accessors do. Is the > > conservative replay acceptable here, or should ISPENDR pay that > > synchronization cost? > > Yes, just kick the target vCPU out and sync the LRs back into the VGIC > state. That's consistent with the approach we're taking everywhere else > where this sort of issue arises. > > If we're lucky the vCPU is just poking at its own redistributor and the > synchronization is free. That makes sense. In my current v2, vgic_mmio_write_spending() uses vgic_access_active_prepare() and vgic_access_active_finish() under config_lock, and drops the extra struct vgic_irq flag. > > > The issue was reproduced with Zephyr, NuttX and RT-Thread guests. On a > > Raspberry Pi 400 host with a GIC-400, each GICv2 guest handled the SPI > > once before the fix and twice afterwards. > > Have you configured these guests in such a way to reproduce the issue? > What exactly are they doing that is susceptible to this issue? > Yes, the runs used a small test harness in each guest. Each test configures unused SPI 150 as level-sensitive, pends it from thread context, and pends it once more from the ISR before deactivation: - Zephyr (qemu_cortex_a53): k_irq_set_pending() -> GICD_ISPENDR. - NuttX (qemu-armv8a): up_set_irq_type(IRQ_HIGH_LEVEL) and up_trigger_irq() -> GICD_ISPENDR. - RT-Thread (qemu-virt64-aarch64, pic.gicv2_eoimode=1): rt_pic_irq_set_state_raw() -> GICD_ISPENDR. A driver that hits the same pattern is RT-Thread's components/drivers/mailbox/mailbox-pic.c, which amp.dtsi configures with level-high SPIs and rings via GICD_ISPENDR. pic_mbox_isr() reads MAILBOX_ISTATE once at entry and clears only those bits at exit. Sending on another channel while pic_mbox_isr() is active sets the new MAILBOX_ISTATE bit and writes GICD_ISPENDR. Without this RFC fix, deactivation drops the second pending state on both GICv2 and GICv3 and leaves the new channel bit stuck. Thanks, Karl