From: Conor Dooley <conor@kernel.org>
To: Andy Chiu <andy.chiu@sifive.com>
Cc: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
anup@brainfault.org, atishp@atishpatra.org,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
vineetg@rivosinc.com, greentime.hu@sifive.com,
guoren@linux.alibaba.com, Vincent Chen <vincent.chen@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Eric Biederman <ebiederm@xmission.com>,
Kees Cook <keescook@chromium.org>, Guo Ren <guoren@kernel.org>,
Heiko Stuebner <heiko@sntech.de>,
Conor Dooley <conor.dooley@microchip.com>,
Nick Knight <nick.knight@sifive.com>,
Sunil V L <sunilvl@ventanamicro.com>,
Kefeng Wang <wangkefeng.wang@huawei.com>,
Zong Li <zong.li@sifive.com>,
Andrew Bresticker <abrestic@rivosinc.com>,
Al Viro <viro@zeniv.linux.org.uk>
Subject: Re: [PATCH -next v14 14/19] riscv: signal: Report signal frame size to userspace via auxv
Date: Wed, 1 Mar 2023 19:21:27 +0000 [thread overview]
Message-ID: <b004ddc6-ec0f-4c7f-8201-df870bf0a86c@spud> (raw)
In-Reply-To: <20230224170118.16766-15-andy.chiu@sifive.com>
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On Fri, Feb 24, 2023 at 05:01:13PM +0000, Andy Chiu wrote:
> From: Vincent Chen <vincent.chen@sifive.com>
>
> The vector register belongs to the signal context. They need to be stored
> and restored as entering and leaving the signal handler. According to the
> V-extension specification, the maximum length of the vector registers can
> be 2^(XLEN-1). Hence, if userspace refers to the MINSIGSTKSZ to create a
> sigframe, it may not be enough. To resolve this problem, this patch refers
> to the commit 94b07c1f8c39c
> ("arm64: signal: Report signal frame size to userspace via auxv") to enable
> userspace to know the minimum required sigframe size through the auxiliary
> vector and use it to allocate enough memory for signal context.
>
> Note that auxv always reports size of the sigframe as if V exists for
> all starting processes, whenever the kernel has CONFIG_RISCV_ISA_V. The
> reason is that users usually reference this value to allocate an
> alternative signal stack, and the user may use V anytime. So the user
> must reserve a space for V-context in sigframe in case that the signal
> handler invokes after the kernel allocating V.
>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
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next prev parent reply other threads:[~2023-03-01 19:21 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-24 17:00 [PATCH -next v14 00/19] riscv: Add vector ISA support Andy Chiu
2023-02-24 17:01 ` [PATCH -next v14 01/19] riscv: Rename __switch_to_aux -> fpu Andy Chiu
2023-02-28 21:56 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 02/19] riscv: Extending cpufeature.c to detect V-extension Andy Chiu
2023-02-28 22:07 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 03/19] riscv: Add new csr defines related to vector extension Andy Chiu
2023-02-28 22:31 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 04/19] riscv: Clear vector regfile on bootup Andy Chiu
2023-02-28 22:17 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 05/19] riscv: Disable Vector Instructions for kernel itself Andy Chiu
2023-02-24 17:01 ` [PATCH -next v14 06/19] riscv: Introduce Vector enable/disable helpers Andy Chiu
2023-02-28 22:36 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 07/19] riscv: Introduce riscv_v_vsize to record size of Vector context Andy Chiu
2023-02-28 22:38 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 08/19] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu
2023-02-28 23:00 ` Conor Dooley
2023-03-15 4:00 ` Andy Chiu
2023-03-02 11:12 ` Björn Töpel
2023-03-15 4:05 ` Andy Chiu
2023-02-24 17:01 ` [PATCH -next v14 09/19] riscv: Add task switch support for vector Andy Chiu
2023-03-01 16:41 ` Conor Dooley
2023-03-01 16:57 ` Björn Töpel
2023-03-02 11:07 ` Björn Töpel
2023-02-24 17:01 ` [PATCH -next v14 10/19] riscv: Allocate user's vector context in the first-use trap Andy Chiu
2023-03-01 16:53 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 11/19] riscv: Add ptrace vector support Andy Chiu
2023-03-01 17:29 ` Conor Dooley
2023-03-02 11:27 ` Björn Töpel
2023-03-14 10:39 ` Andy Chiu
2023-03-14 10:44 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 12/19] riscv: signal: check fp-reserved words unconditionally Andy Chiu
2023-03-01 17:56 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 13/19] riscv: signal: Add sigcontext save/restore for vector Andy Chiu
2023-03-01 18:27 ` Conor Dooley
2023-03-02 12:42 ` Björn Töpel
2023-02-24 17:01 ` [PATCH -next v14 14/19] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu
2023-03-01 19:21 ` Conor Dooley [this message]
2023-03-02 12:47 ` Björn Töpel
2023-02-24 17:01 ` [PATCH -next v14 15/19] riscv: signal: validate altstack to reflect Vector Andy Chiu
2023-03-01 21:00 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 16/19] riscv: prevent stack corruption by reserving task_pt_regs(p) early Andy Chiu
2023-03-01 21:34 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 17/19] riscv: kvm: Add V extension to KVM ISA Andy Chiu
2023-03-01 21:38 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 18/19] riscv: KVM: Add vector lazy save/restore support Andy Chiu
2023-02-24 17:01 ` [PATCH -next v14 19/19] riscv: Enable Vector code to be built Andy Chiu
2023-02-24 21:35 ` kernel test robot
2023-02-25 1:33 ` kernel test robot
2023-03-01 18:00 ` Nathan Chancellor
2023-03-01 18:44 ` Conor Dooley
2023-02-25 8:28 ` kernel test robot
2023-02-27 10:18 ` Conor Dooley
2023-02-27 13:40 ` Darius Rad
2023-02-27 13:58 ` Conor Dooley
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