[kvm-unit-tests PATCH v3 2/9] s390x: Define the PSW bits

Pierre Morel
2019-12-06T16:26:50Z

Let's define the PSW bits explicitly, it will clarify their
usage.

Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
---
lib/s390x/asm/arch_def.h | 127 +++++++++++++++++++++------------------
s390x/cstart64.S | 13 ++--
2 files changed, 74 insertions(+), 66 deletions(-)

diff --git a/lib/s390x/asm/arch_def.h b/lib/s390x/asm/arch_def.h
index cf6e1ca..1293640 100644
--- a/lib/s390x/asm/arch_def.h
+++ b/lib/s390x/asm/arch_def.h
@@ -10,20 +10,81 @@
#ifndef _ASM_S390X_ARCH_DEF_H_
#define _ASM_S390X_ARCH_DEF_H_

-struct psw {
- uint64_t mask;
- uint64_t addr;
-};
-
#define PSW_MASK_EXT 0x0100000000000000UL
#define PSW_MASK_DAT 0x0400000000000000UL
#define PSW_MASK_PSTATE 0x0001000000000000UL
+#define PSW_MASK_IO 0x0200000000000000
+#define PSW_MASK_EA 0x0000000100000000
+#define PSW_MASK_BA 0x0000000080000000
+
+#define PSW_EXCEPTION_MASK (PSW_MASK_EA|PSW_MASK_BA)

#define CR0_EXTM_SCLP 0X0000000000000200UL
#define CR0_EXTM_EXTC 0X0000000000002000UL
#define CR0_EXTM_EMGC 0X0000000000004000UL
#define CR0_EXTM_MASK 0X0000000000006200UL

+#define PGM_INT_CODE_OPERATION 0x01
+#define PGM_INT_CODE_PRIVILEGED_OPERATION 0x02
+#define PGM_INT_CODE_EXECUTE 0x03
+#define PGM_INT_CODE_PROTECTION 0x04
+#define PGM_INT_CODE_ADDRESSING 0x05
+#define PGM_INT_CODE_SPECIFICATION 0x06
+#define PGM_INT_CODE_DATA 0x07
+#define PGM_INT_CODE_FIXED_POINT_OVERFLOW 0x08
+#define PGM_INT_CODE_FIXED_POINT_DIVIDE 0x09
+#define PGM_INT_CODE_DECIMAL_OVERFLOW 0x0a
+#define PGM_INT_CODE_DECIMAL_DIVIDE 0x0b
+#define PGM_INT_CODE_HFP_EXPONENT_OVERFLOW 0x0c
+#define PGM_INT_CODE_HFP_EXPONENT_UNDERFLOW 0x0d
+#define PGM_INT_CODE_HFP_SIGNIFICANCE 0x0e
+#define PGM_INT_CODE_HFP_DIVIDE 0x0f
+#define PGM_INT_CODE_SEGMENT_TRANSLATION 0x10
+#define PGM_INT_CODE_PAGE_TRANSLATION 0x11
+#define PGM_INT_CODE_TRANSLATION_SPEC 0x12
+#define PGM_INT_CODE_SPECIAL_OPERATION 0x13
+#define PGM_INT_CODE_OPERAND 0x15
+#define PGM_INT_CODE_TRACE_TABLE 0x16
+#define PGM_INT_CODE_VECTOR_PROCESSING 0x1b
+#define PGM_INT_CODE_SPACE_SWITCH_EVENT 0x1c
+#define PGM_INT_CODE_HFP_SQUARE_ROOT 0x1d
+#define PGM_INT_CODE_PC_TRANSLATION_SPEC 0x1f
+#define PGM_INT_CODE_AFX_TRANSLATION 0x20
+#define PGM_INT_CODE_ASX_TRANSLATION 0x21
+#define PGM_INT_CODE_LX_TRANSLATION 0x22
+#define PGM_INT_CODE_EX_TRANSLATION 0x23
+#define PGM_INT_CODE_PRIMARY_AUTHORITY 0x24
+#define PGM_INT_CODE_SECONDARY_AUTHORITY 0x25
+#define PGM_INT_CODE_LFX_TRANSLATION 0x26
+#define PGM_INT_CODE_LSX_TRANSLATION 0x27
+#define PGM_INT_CODE_ALET_SPECIFICATION 0x28
+#define PGM_INT_CODE_ALEN_TRANSLATION 0x29
+#define PGM_INT_CODE_ALE_SEQUENCE 0x2a
+#define PGM_INT_CODE_ASTE_VALIDITY 0x2b
+#define PGM_INT_CODE_ASTE_SEQUENCE 0x2c
+#define PGM_INT_CODE_EXTENDED_AUTHORITY 0x2d
+#define PGM_INT_CODE_LSTE_SEQUENCE 0x2e
+#define PGM_INT_CODE_ASTE_INSTANCE 0x2f
+#define PGM_INT_CODE_STACK_FULL 0x30
+#define PGM_INT_CODE_STACK_EMPTY 0x31
+#define PGM_INT_CODE_STACK_SPECIFICATION 0x32
+#define PGM_INT_CODE_STACK_TYPE 0x33
+#define PGM_INT_CODE_STACK_OPERATION 0x34
+#define PGM_INT_CODE_ASCE_TYPE 0x38
+#define PGM_INT_CODE_REGION_FIRST_TRANS 0x39
+#define PGM_INT_CODE_REGION_SECOND_TRANS 0x3a
+#define PGM_INT_CODE_REGION_THIRD_TRANS 0x3b
+#define PGM_INT_CODE_MONITOR_EVENT 0x40
+#define PGM_INT_CODE_PER 0x80
+#define PGM_INT_CODE_CRYPTO_OPERATION 0x119
+#define PGM_INT_CODE_TX_ABORTED_EVENT 0x200
+
+#ifndef __ASSEMBLER__
+struct psw {
+ uint64_t mask;
+ uint64_t addr;
+};
+
struct lowcore {
uint8_t pad_0x0000[0x0080 - 0x0000]; /* 0x0000 */
uint32_t ext_int_param; /* 0x0080 */
@@ -101,61 +162,6 @@ struct lowcore {
} __attribute__ ((__packed__));
_Static_assert(sizeof(struct lowcore) == 0x1900, "Lowcore size");

-#define PGM_INT_CODE_OPERATION 0x01
-#define PGM_INT_CODE_PRIVILEGED_OPERATION 0x02
-#define PGM_INT_CODE_EXECUTE 0x03
-#define PGM_INT_CODE_PROTECTION 0x04
-#define PGM_INT_CODE_ADDRESSING 0x05
-#define PGM_INT_CODE_SPECIFICATION 0x06
-#define PGM_INT_CODE_DATA 0x07
-#define PGM_INT_CODE_FIXED_POINT_OVERFLOW 0x08
-#define PGM_INT_CODE_FIXED_POINT_DIVIDE 0x09
-#define PGM_INT_CODE_DECIMAL_OVERFLOW 0x0a
-#define PGM_INT_CODE_DECIMAL_DIVIDE 0x0b
-#define PGM_INT_CODE_HFP_EXPONENT_OVERFLOW 0x0c
-#define PGM_INT_CODE_HFP_EXPONENT_UNDERFLOW 0x0d
-#define PGM_INT_CODE_HFP_SIGNIFICANCE 0x0e
-#define PGM_INT_CODE_HFP_DIVIDE 0x0f
-#define PGM_INT_CODE_SEGMENT_TRANSLATION 0x10
-#define PGM_INT_CODE_PAGE_TRANSLATION 0x11
-#define PGM_INT_CODE_TRANSLATION_SPEC 0x12
-#define PGM_INT_CODE_SPECIAL_OPERATION 0x13
-#define PGM_INT_CODE_OPERAND 0x15
-#define PGM_INT_CODE_TRACE_TABLE 0x16
-#define PGM_INT_CODE_VECTOR_PROCESSING 0x1b
-#define PGM_INT_CODE_SPACE_SWITCH_EVENT 0x1c
-#define PGM_INT_CODE_HFP_SQUARE_ROOT 0x1d
-#define PGM_INT_CODE_PC_TRANSLATION_SPEC 0x1f
-#define PGM_INT_CODE_AFX_TRANSLATION 0x20
-#define PGM_INT_CODE_ASX_TRANSLATION 0x21
-#define PGM_INT_CODE_LX_TRANSLATION 0x22
-#define PGM_INT_CODE_EX_TRANSLATION 0x23
-#define PGM_INT_CODE_PRIMARY_AUTHORITY 0x24
-#define PGM_INT_CODE_SECONDARY_AUTHORITY 0x25
-#define PGM_INT_CODE_LFX_TRANSLATION 0x26
-#define PGM_INT_CODE_LSX_TRANSLATION 0x27
-#define PGM_INT_CODE_ALET_SPECIFICATION 0x28
-#define PGM_INT_CODE_ALEN_TRANSLATION 0x29
-#define PGM_INT_CODE_ALE_SEQUENCE 0x2a
-#define PGM_INT_CODE_ASTE_VALIDITY 0x2b
-#define PGM_INT_CODE_ASTE_SEQUENCE 0x2c
-#define PGM_INT_CODE_EXTENDED_AUTHORITY 0x2d
-#define PGM_INT_CODE_LSTE_SEQUENCE 0x2e
-#define PGM_INT_CODE_ASTE_INSTANCE 0x2f
-#define PGM_INT_CODE_STACK_FULL 0x30
-#define PGM_INT_CODE_STACK_EMPTY 0x31
-#define PGM_INT_CODE_STACK_SPECIFICATION 0x32
-#define PGM_INT_CODE_STACK_TYPE 0x33
-#define PGM_INT_CODE_STACK_OPERATION 0x34
-#define PGM_INT_CODE_ASCE_TYPE 0x38
-#define PGM_INT_CODE_REGION_FIRST_TRANS 0x39
-#define PGM_INT_CODE_REGION_SECOND_TRANS 0x3a
-#define PGM_INT_CODE_REGION_THIRD_TRANS 0x3b
-#define PGM_INT_CODE_MONITOR_EVENT 0x40
-#define PGM_INT_CODE_PER 0x80
-#define PGM_INT_CODE_CRYPTO_OPERATION 0x119
-#define PGM_INT_CODE_TX_ABORTED_EVENT 0x200
-
struct cpuid {
uint64_t version : 8;
uint64_t id : 24;
@@ -271,4 +277,5 @@ static inline int stsi(void *addr, int fc, int sel1, int sel2)
return cc;
}

+#endif /* __ASSEMBLER__ */
#endif
diff --git a/s390x/cstart64.S b/s390x/cstart64.S
index ff05f9b..f292ed6 100644
--- a/s390x/cstart64.S
+++ b/s390x/cstart64.S
@@ -12,6 +12,7 @@
*/
#include <asm/asm-offsets.h>
#include <asm/sigp.h>
+#include <asm/arch_def.h>

.section .init

@@ -216,17 +217,17 @@ svc_int:
reset_psw:
.quad 0x0008000180000000
initial_psw:
- .quad 0x0000000180000000, clear_bss_start
+ .quad PSW_EXCEPTION_MASK, clear_bss_start
pgm_int_psw:
- .quad 0x0000000180000000, pgm_int
+ .quad PSW_EXCEPTION_MASK, pgm_int
ext_int_psw:
- .quad 0x0000000180000000, ext_int
+ .quad PSW_EXCEPTION_MASK, ext_int
mcck_int_psw:
- .quad 0x0000000180000000, mcck_int
+ .quad PSW_EXCEPTION_MASK, mcck_int
io_int_psw:
- .quad 0x0000000180000000, io_int
+ .quad PSW_EXCEPTION_MASK, io_int
svc_int_psw:
- .quad 0x0000000180000000, svc_int
+ .quad PSW_EXCEPTION_MASK, svc_int
initial_cr0:
/* enable AFP-register control, so FP regs (+BFP instr) can be used */
.quad 0x0000000000040000
--
2.17.0