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From: "Nikunj A. Dadhania" <nikunj@amd.com>
To: <pbonzini@redhat.com>, <seanjc@google.com>
Cc: <bp@alien8.de>, <joao.m.martins@oracle.com>,
	<kai.huang@intel.com>, <kvm@vger.kernel.org>,
	<thomas.lendacky@amd.com>, <yosry@kernel.org>
Subject: Re: [PATCH v7.1] KVM: SVM: Add Page modification logging support
Date: Mon, 13 Jul 2026 11:42:41 +0530	[thread overview]
Message-ID: <b5f2e0a4-09c1-43d7-b700-c8760d70b195@amd.com> (raw)
In-Reply-To: <20260529063833.1660791-1-nikunj@amd.com>



On 5/29/2026 12:08 PM, Nikunj A Dadhania wrote:
> Currently, dirty logging relies on write protecting guest memory and
> marking dirty GFNs during subsequent write faults. This method works but
> incurs overhead due to additional write faults for each dirty GFN.
> 
> Implement support for the Page Modification Logging (PML) feature, a
> hardware-assisted method for efficient dirty logging. PML automatically
> logs dirty GPA[51:12] to a 4K buffer when the CPU sets NPT D-bits. Two new
> VMCB fields are utilized: PML_ADDR and PML_INDEX. The PML_INDEX is
> initialized to 511 (8 bytes per GPA entry), and the CPU decreases the
> PML_INDEX after logging each GPA. When the PML buffer is full, a
> VMEXIT(PML_FULL) with exit code 0x407 is generated.
> 
> Since PML_INDEX in the VMCB control area remains valid after an intercepted
> SHUTDOWN, only initialize it on reset and leave it unchanged on INIT to
> avoid discarding already-logged entries that haven't been flushed.
> 
> PML operates on guest physical addresses at the NPT level, tracking D-bit
> updates in page tables rather than memory content. This allows it to work
> identically for normal and confidential computing guests
> (SEV/SEV-ES/SEV-SNP), enabling cpu_dirty_log_size to be set uniformly for
> all AMD VMs without special-casing encrypted guests.
> 
> Use vmcb01 directly when updating PML controls to ensure L1's state
> remains correct, as svm->vmcb points to vmcb02 when L2 is active.
> 
> PML is not enabled in hardware for nested guests; treat PML_FULL as
> unexpected exits.
> 
> Add a new module parameter to enable/disable PML, and enable it by default
> when supported.
> 
> Acked-by: Kai Huang <kai.huang@intel.com>
> Signed-off-by: Nikunj A Dadhania <nikunj@amd.com>
> ---
> 
> Sending updated 7/7 patch here, rather than reposting the full series.
> 
> Sean, any remaining comments? Happy to send v8 if needed.

A gentle reminder

> v7 -> v7.1:
> * Drop redundant pml_addr=0 in nested_vmcb02_prepare_control() (Yosry)
> * Fix misleading comment, pml_index=-1 is hardening not stale-data cleanup (Yosry, Sean)
> * Route nested SVM_EXIT_PML_FULL to KVM and treat it as unexpected exit (Sean)

Regards,
Nikunj


      reply	other threads:[~2026-07-13  6:13 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-18  4:59 [PATCH v7 0/7] KVM: SVM: Add Page Modification Logging (PML) support Nikunj A Dadhania
2026-05-18  4:59 ` [PATCH v7 1/7] KVM: VMX: Pass @vcpu, not @vmx to init_vmcs() Nikunj A Dadhania
2026-05-18 11:35   ` Huang, Kai
2026-05-18  4:59 ` [PATCH v7 2/7] KVM: x86: Move PML page to common vcpu arch structure Nikunj A Dadhania
2026-05-18  4:59 ` [PATCH v7 3/7] KVM: x86: Carve out PML flush routine Nikunj A Dadhania
2026-05-18  4:59 ` [PATCH v7 4/7] KVM: VMX: Use cpu_dirty_log_size instead of enable_pml for PML checks Nikunj A Dadhania
2026-05-18  4:59 ` [PATCH v7 5/7] x86/cpufeatures: Add Page modification logging Nikunj A Dadhania
2026-05-18  4:59 ` [PATCH v7 6/7] KVM: SVM: Use BIT_ULL for 64-bit misc_ctl bit definitions Nikunj A Dadhania
2026-05-18  4:59 ` [PATCH v7 7/7] KVM: SVM: Add Page modification logging support Nikunj A Dadhania
2026-05-18 17:12   ` Yosry Ahmed
2026-05-18 18:55     ` Sean Christopherson
2026-05-18 19:14       ` Yosry Ahmed
2026-05-18 19:25       ` Yosry Ahmed
2026-05-19 14:46       ` Nikunj A. Dadhania
2026-05-29  6:38         ` [PATCH v7.1] " Nikunj A Dadhania
2026-07-13  6:12           ` Nikunj A. Dadhania [this message]

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