Re: [PATCH v16 51/51] KVM: VMX: Make CR4.CET a guest owned bit

Binbin Wu
2025-09-22T08:34:12Z

On 9/20/2025 6:32 AM, Sean Christopherson wrote:
> From: Mathias Krause <minipli@grsecurity.net>
>
> Make CR4.CET a guest-owned bit under VMX by extending
> KVM_POSSIBLE_CR4_GUEST_BITS accordingly.
>
> There's no need to intercept changes to CR4.CET, as it's neither
> included in KVM's MMU role bits, nor does KVM specifically care about
> the actual value of a (nested) guest's CR4.CET value, beside for
> enforcing architectural constraints, i.e. make sure that CR0.WP=1 if
> CR4.CET=1.
>
> Intercepting writes to CR4.CET is particularly bad for grsecurity
> kernels with KERNEXEC or, even worse, KERNSEAL enabled. These features
> heavily make use of read-only kernel objects and use a cpu-local CR0.WP
> toggle to override it, when needed. Under a CET-enabled kernel, this
> also requires toggling CR4.CET, hence the motivation to make it
> guest-owned.
>
> Using the old test from [1] gives the following runtime numbers (perf
> stat -r 5 ssdd 10 50000):
>
> * grsec guest on linux-6.16-rc5 + cet patches:
> 2.4647 +- 0.0706 seconds time elapsed ( +- 2.86% )
>
> * grsec guest on linux-6.16-rc5 + cet patches + CR4.CET guest-owned:
> 1.5648 +- 0.0240 seconds time elapsed ( +- 1.53% )
>
> Not only does not intercepting CR4.CET make the test run ~35% faster,
> it's also more stable with less fluctuation due to fewer VMEXITs.
>
> Therefore, make CR4.CET a guest-owned bit where possible.
>
> This change is VMX-specific, as SVM has no such fine-grained control
> register intercept control.
>
> If KVM's assumptions regarding MMU role handling wrt. a guest's CR4.CET
> value ever change, the BUILD_BUG_ON()s related to KVM_MMU_CR4_ROLE_BITS
> and KVM_POSSIBLE_CR4_GUEST_BITS will catch that early.
>
> Link: https://lore.kernel.org/kvm/20230322013731.102955-1-minipli@grsecurity.net/ [1]
> Reviewed-by: Chao Gao <chao.gao@intel.com>
> Signed-off-by: Mathias Krause <minipli@grsecurity.net>
> Signed-off-by: Sean Christopherson <seanjc@google.com>

Reviewed-by: Binbin Wu <binbin.wu@linux.intel.com>

> ---
> arch/x86/kvm/kvm_cache_regs.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/kvm/kvm_cache_regs.h b/arch/x86/kvm/kvm_cache_regs.h
> index 36a8786db291..8ddb01191d6f 100644
> --- a/arch/x86/kvm/kvm_cache_regs.h
> +++ b/arch/x86/kvm/kvm_cache_regs.h
> @@ -7,7 +7,8 @@
> #define KVM_POSSIBLE_CR0_GUEST_BITS (X86_CR0_TS | X86_CR0_WP)
> #define KVM_POSSIBLE_CR4_GUEST_BITS \
> (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
> - | X86_CR4_OSXMMEXCPT | X86_CR4_PGE | X86_CR4_TSD | X86_CR4_FSGSBASE)
> + | X86_CR4_OSXMMEXCPT | X86_CR4_PGE | X86_CR4_TSD | X86_CR4_FSGSBASE \
> + | X86_CR4_CET)
>
> #define X86_CR0_PDPTR_BITS (X86_CR0_CD | X86_CR0_NW | X86_CR0_PG)
> #define X86_CR4_TLBFLUSH_BITS (X86_CR4_PGE | X86_CR4_PCIDE | X86_CR4_PAE | X86_CR4_SMEP)