From: "André Przywara" <andre.przywara@arm.com>
To: Alexandru Elisei <alexandru.elisei@arm.com>,
drjones@redhat.com, kvm@vger.kernel.org,
kvmarm@lists.cs.columbia.edu
Cc: eric.auger@redhat.com, yuzenghui@huawei.com
Subject: Re: [kvm-unit-tests PATCH v2 11/12] lib: arm64: gic-v3-its: Add wmb() barrier before INT command
Date: Fri, 18 Dec 2020 18:36:53 +0000 [thread overview]
Message-ID: <bb0faa84-d12f-05b7-9913-155ebfcb3073@arm.com> (raw)
In-Reply-To: <20201217141400.106137-12-alexandru.elisei@arm.com>
On 17/12/2020 14:13, Alexandru Elisei wrote:
> The ITS tests use the INT command like an SGI. The its_send_int() function
> kicks a CPU and then the test checks that the interrupt was observed as
> expected in check_lpi_stats(). This is done by using lpi_stats.observed and
> lpi_stats.expected, where the target CPU only writes to lpi_stats.observed,
> and the source CPU reads it and compares the values with
> lpi_stats.expected.
>
> The fact that the target CPU doesn't read data written by the source CPU
> means that we don't need to do inter-processor memory synchronization
> for that between the two at the moment.
>
> The acked array is used by its-pending-migration test, but the reset value
> for acked (zero) is the same as the initialization value for static
> variables, so memory synchronization is again not needed.
>
> However, that is all about to change when we modify all ITS tests to use
> the same functions as the IPI tests. Add a write memory barrier to
> its_send_int(), similar to the gicv3_ipi_send_mask(), which has similar
> semantics.
I agree to the requirement for having the barrier, but am not sure this
is the right place. Wouldn't it be better to have the barrier in the
callers?
Besides: This command is written to the command queue (in normal
memory), then we notify the ITS via an MMIO writeq. And this one has a
"wmb" barrier already (though for other reasons).
Cheers,
Andre
>
> Suggested-by: Auger Eric <eric.auger@redhat.com>
> Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
> ---
> lib/arm64/gic-v3-its-cmd.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/lib/arm64/gic-v3-its-cmd.c b/lib/arm64/gic-v3-its-cmd.c
> index 34574f71d171..32703147ee85 100644
> --- a/lib/arm64/gic-v3-its-cmd.c
> +++ b/lib/arm64/gic-v3-its-cmd.c
> @@ -385,6 +385,12 @@ void __its_send_int(struct its_device *dev, u32 event_id, bool verbose)
> {
> struct its_cmd_desc desc;
>
> + /*
> + * The INT command is used by tests as an IPI. Ensure stores to Normal
> + * memory are visible to other CPUs before sending the LPI.
> + */
> + wmb();
> +
> desc.its_int_cmd.dev = dev;
> desc.its_int_cmd.event_id = event_id;
> desc.verbose = verbose;
>
next prev parent reply other threads:[~2020-12-18 18:37 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-17 14:13 [kvm-unit-tests PATCH v2 00/12] GIC fixes and improvements Alexandru Elisei
2020-12-17 14:13 ` [kvm-unit-tests PATCH v2 01/12] lib: arm/arm64: gicv3: Add missing barrier when sending IPIs Alexandru Elisei
2020-12-18 12:03 ` André Przywara
2020-12-17 14:13 ` [kvm-unit-tests PATCH v2 02/12] lib: arm/arm64: gicv2: " Alexandru Elisei
2020-12-17 14:13 ` [kvm-unit-tests PATCH v2 03/12] arm/arm64: gic: Remove SMP synchronization from ipi_clear_active_handler() Alexandru Elisei
2020-12-18 12:04 ` André Przywara
2020-12-17 14:13 ` [kvm-unit-tests PATCH v2 04/12] arm/arm64: gic: Remove unnecessary synchronization with stats_reset() Alexandru Elisei
2020-12-17 14:13 ` [kvm-unit-tests PATCH v2 05/12] arm/arm64: gic: Use correct memory ordering for the IPI test Alexandru Elisei
2020-12-18 12:04 ` André Przywara
2020-12-17 14:13 ` [kvm-unit-tests PATCH v2 06/12] arm/arm64: gic: Check spurious and bad_sender in the active test Alexandru Elisei
2020-12-17 14:13 ` [kvm-unit-tests PATCH v2 07/12] arm/arm64: gic: Wait for writes to acked or spurious to complete Alexandru Elisei
2020-12-17 14:13 ` [kvm-unit-tests PATCH v2 08/12] arm/arm64: gic: Split check_acked() into two functions Alexandru Elisei
2020-12-18 15:52 ` André Przywara
2021-01-25 17:27 ` Alexandru Elisei
2021-01-27 15:10 ` Andre Przywara
2021-01-27 16:00 ` Alexandru Elisei
2021-02-16 18:04 ` Andre Przywara
2020-12-17 14:13 ` [kvm-unit-tests PATCH v2 09/12] arm/arm64: gic: Make check_acked() more generic Alexandru Elisei
2020-12-18 15:52 ` André Przywara
2020-12-17 14:13 ` [kvm-unit-tests PATCH v2 10/12] arm64: gic: its-trigger: Don't trigger the LPI while it is pending Alexandru Elisei
2020-12-18 18:15 ` André Przywara
2021-01-25 16:57 ` Alexandru Elisei
2020-12-17 14:13 ` [kvm-unit-tests PATCH v2 11/12] lib: arm64: gic-v3-its: Add wmb() barrier before INT command Alexandru Elisei
2020-12-18 18:36 ` André Przywara [this message]
2021-01-25 15:16 ` Alexandru Elisei
2020-12-17 14:14 ` [kvm-unit-tests PATCH v2 12/12] arm64: gic: Use IPI test checking for the LPI tests Alexandru Elisei
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=bb0faa84-d12f-05b7-9913-155ebfcb3073@arm.com \
--to=andre.przywara@arm.com \
--cc=alexandru.elisei@arm.com \
--cc=drjones@redhat.com \
--cc=eric.auger@redhat.com \
--cc=kvm@vger.kernel.org \
--cc=kvmarm@lists.cs.columbia.edu \
--cc=yuzenghui@huawei.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox