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Peter Anvin" , "Peter Zijlstra (Intel)" , Borislav Petkov , Dave Hansen , Ingo Molnar , "Mathieu Desnoyers" , Paolo Bonzini , Sean Christopherson , "Thomas Gleixner" , , , , , Subject: Re: [PATCH v3 1/2] x86/uaccess: Extend CMPXCHG user helpers to 128-bit operands Content-Language: en-US To: Uros Bizjak , Dave Hansen References: <20260826070004.8100-1-sarunkod@amd.com> <20260826070004.8100-2-sarunkod@amd.com> From: Sairaj Kodilkar In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E7E:EE_|BL1PR12MB5729:EE_ X-MS-Office365-Filtering-Correlation-Id: efd6b4bf-c140-46f3-6e56-08df037600de X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|376014|30052699003|7416014|1800799024|82310400026|36860700016|18002099003|22082099003|11063799006|56012099006|13003099007|3023799007|4143699003|10067099003; X-Microsoft-Antispam-Message-Info: dQu7J4Feuq0kU9CC3mlOZDVi3FyXhkqmJ9Us3TXlATJhUfPjlsMLk5/pophPoJA7Nz5Ry++UCS6K7SQAgxEVv5MEt5BmETaOj72k/Ode86k4dQ/oC1b2JP9K/GjdPDuWedGSmpuXTHXe/+5dlVHbHNZVR2Qkz6FKwbAeRIY9ZypBsP0cVW/3YkeCrZlkxD9tbZtPb9zE6HQkkVXbCONEE++bzBoq4mCVkThdkLEhLeDj+EsajJRGjblnW/vOmuhO/NTOC8D5mc2qcxYuJ7wZG7OF9XD6TRzuKRFw+L0GrEaOZwFBGVr2Gh5A8/dS7IJoL5E8xLYoL9OzujAlS+aweinXWEAVIW/k3soNUeAconrtSg0nIkGK+xklkNqrfjoj6uTBa2bW1mCyMGnDotp8NdoJ60nvxYSRvqXu1bPWwd8IhcOSjLLPaPHH0R603NJmB1QFc5hgbRbw0SWhLRHDaaJuDM/JSLOkK9yo+e7IfnT7Het7uVH4C579Y7yqLdu/xGQcEen7nGVZ4zHgeNrWYf1UADzSobxrbjn2Y2kU4nr/Mj1aiDiF6unArFmYx3lKR1Szejt9STemN7xOuYjrhtVWthX15em5Y4CTSkzmTwyoIQWYYjmnwQ5StB3QSfpDOyTFNYTEy9DPdC548A798w== X-Forefront-Antispam-Report: CIP:149.199.90.133;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:unknown-90-133.xilinx.com;CAT:NONE;SFS:(13230040)(23010399003)(376014)(30052699003)(7416014)(1800799024)(82310400026)(36860700016)(18002099003)(22082099003)(11063799006)(56012099006)(13003099007)(3023799007)(4143699003)(10067099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: EUbkR+OLeKchLVI/LtHcziOvnmbuHKy0eUYecobG/Ae8Y/fw1yOaug3lVCL3s8oIuYiP6ai2yTOAI9TN9WozzbpgRI+yTEDSVtdG2D3mZP9dRd7J7KUF0j/Zlyh8WnoTcFWVOz4fcPZq555WkQRdIGuVZpMGj7t3s7PvjYUyCabtmprXEfpKaBau3KnAzSY8XcYOwspqhzhGMalA3Xvm5eZxbaXbS5zk5H+xeKIb+pzIfQ2RPJhhDBKAFBQGqzafpTTmYslpX645Sfu1qtySDfw0/qpp1i/pPoIsDBA2Rxx3FG0wAuykUeiwoKBek2T7ZTfyLWuohfMzf2VDMdnfjNuYYUozXi2PZxEBMi/01+QbzGb9zQlUhETC8fnNJOT9v0+MCe1UeJxFrg+wmns3zC4aTbEu4XYYPATY6HsijIpBMjy5wGkkbXXc6Iw1Hjxx X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Aug 2026 13:29:06.4215 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: efd6b4bf-c140-46f3-6e56-08df037600de X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[149.199.90.133];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E7E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5729 On 8/26/2026 6:49 PM, Uros Bizjak wrote: > [You don't often get email from ubizjak@gmail.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ] > > On Wed, Aug 26, 2026 at 2:30 PM Dave Hansen wrote: >> >> On 8/26/26 00:00, Sairaj Kodilkar wrote: >>> Extend the existing user CMPXCHG helpers to support 16-byte operands on >>> x86-64, using LOCK_PREFIX "cmpxchg16b". This mirrors the existing >>> __try_cmpxchg64_user_asm() / cmpxchg8b path provided for 32-bit kernels, >>> where KVM needs an atomic compare-exchange wider than the generic >>> cmpxchg helper can provide. >> >> Please take a good look at the Sashiko review: >> >> https://sashiko.dev/#/patchset/20260826070004.8100-2-sarunkod%40amd.com >> >> It looks like the "A" constraint isn't one that you can cleanly mirror >> from cmpxchg8b => cmpxchg16b. > > Actually, "+A" will work for 64bit targets, as long as the variable is > 128-bit. The comment in asm.h applies to 64-bit values, where on > 32-bit targets they fit in eax *and* edx, while on 64-bit targets, the > 64-bit values fit into rax *or* rdx. > > This is documented in GCC documentation: > > ‘A’ > The ‘a’ and ‘d’ registers. This class is used for > instructions that return double word results in the ‘ax:dx’ > register pair. Single word values will be allocated either in > ‘ax’ or ‘dx’. > > And can be confirmed with e.g.: > > __int128 val; > > void foo (void) > { > __int128 _v = val; > asm volatile ("" : "+A" (_v)); > val = _v; > } > > which will fail compilation with -ffixed-rax or -ffixed-rdx. > > That said, the approach with union of two 64-bit halves can lead to > slightly better code, because the compiler splits the value earlier in > the compilation pipeline. > >> Uros, any chance you can give these a good once-over? This seems to be >> just the kind of thing you've been fixing up lately. It would be nice to >> get them right the first time. > > Based on the above explanation, these *can* be copied from 32-bit asm > patterns. Even "q" constraint will include all integer registers on > 64-bit targets. Yep, this is what I was trying to say in my reply to sashiko. Basically +A can be safely used for 64 bit values on 32 bit machines and 128 bit values on 64 bit machines. Also if you prefer split one, I can do that as well. Sairaj > > Uros.