Re: [PATCH 1/2] Enumerate AVX Vector Neural Network instructions

Paolo Bonzini
2021-01-05T11:49:02Z

On 05/01/21 01:49, Yang Zhong wrote:
> From: Kyung Min Park <kyung.min.park@intel.com>
>
> Add AVX version of the Vector Neural Network (VNNI) Instructions.
>
> A processor supports AVX VNNI instructions if CPUID.0x07.0x1:EAX[4] is
> present. The following instructions are available when this feature is
> present.
> 1. VPDPBUS: Multiply and Add Unsigned and Signed Bytes
> 2. VPDPBUSDS: Multiply and Add Unsigned and Signed Bytes with Saturation
> 3. VPDPWSSD: Multiply and Add Signed Word Integers
> 4. VPDPWSSDS: Multiply and Add Signed Integers with Saturation
>
> The only in-kernel usage of this is kvm passthrough. The CPU feature
> flag is shown as "avx_vnni" in /proc/cpuinfo.
>
> This instruction is currently documented in the latest "extensions"
> manual (ISE). It will appear in the "main" manual (SDM) in the future.
>
> Signed-off-by: Kyung Min Park <kyung.min.park@intel.com>
> Signed-off-by: Yang Zhong <yang.zhong@intel.com>
> Reviewed-by: Tony Luck <tony.luck@intel.com>
> ---
> arch/x86/include/asm/cpufeatures.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index f5ef2d5b9231..d10d9962bd9b 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -293,6 +293,7 @@
> #define X86_FEATURE_PER_THREAD_MBA (11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */
>
> /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
> +#define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
> #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
>
> /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
>

Boris, is it possible to have a topic branch for this patch?