[Bug 220740] Host crash when do PF passthrough to KVM guest with some devices

[bugzilla-daemon@kernel.org]

https://bugzilla.kernel.org/show_bug.cgi?id=220740

--- Comment #6 from Chen, Fan (farrah.chen@intel.com) ---
(In reply to Alex Williamson from comment #5)
> I have an X710, but not a system that can reproduce the issue.
> 
> Also I need to correct my previous statement after untangling the headers. 
> This commit did introduce 8-byte access support for archs including x86_64
> where they don't otherwise defined a ioread/write64 support.  This access
> uses readq/writeq, where previously we'd use pairs or readl/writel.  The
> expectation is that we're more closely matching the access by the guest.
> 
> I'm curious how we're getting into this code for an X710 though, mine shows
> BARs as:
> 
> 03:00.0 Ethernet controller: Intel Corporation Ethernet Controller X710 for
> 10GbE SFP+ (rev 01)
>         Region 0: Memory at 380000000000 (64-bit, prefetchable) [size=8M]
>         Region 3: Memory at 380001800000 (64-bit, prefetchable) [size=32K]
> 
> Those would typically be mapped directly into the KVM address space and not
> fault through QEMU to trigger access through this code.  The MSI-X
> capability lands in BAR3:
> 
>         Capabilities: [70] MSI-X: Enable- Count=129 Masked-
>                 Vector table: BAR=3 offset=00000000
>                 PBA: BAR=3 offset=00001000
> 

Not sure if it is related, but on my systems, different from yours, the MSI-X
capability is "Enable+":
        Capabilities: [70] MSI-X: Enable+ Count=129 Masked-
                Vector table: BAR=3 offset=00000000
                PBA: BAR=3 offset=00001000

And if without this commit(reset to previous commit), I can passthrough X710
successfully with below log in host dmesg:
gnr-sp-2s-605 login: [  129.819630] i40e 0000:b8:00.0: i40e_ptp_stop: removed
PHC on ens26f0np0
[  143.509906] vfio-pci 0000:b8:00.0: resetting
[  143.619051] vfio-pci 0000:b8:00.0: reset done
[  143.624135] vfio-pci 0000:b8:00.0: Masking broken INTx support
[  143.669167] vfio-pci 0000:b8:00.0: resetting
[  143.779059] vfio-pci 0000:b8:00.0: reset done
[  144.392971] vfio-pci 0000:b8:00.0: vfio_bar_restore: reset recovery -
restoring BARs


> Ideally the device follows the PCIe recommendation not to place registers in
> the same page as the vector and pba tables, not doing so could cause this
> access though.  If it were such an access, QEMU could virtualize the MSI-X
> tables on a different BAR with the option x-msix-relocation=bar5 (or bar2).
> 
> If QEMU were using x-no-mmap=on then we could expect this code would be
> used, but that's not specified in the example.

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