[PATCH 0/4] Advertise CPUID for new instructions in Clearwater Forest

[PATCH 0/4] Advertise CPUID for new instructions in Clearwater Forest

[Tao Su]

Latest Intel platform Clearwater Forest has introduced new instructions
for SHA512, SM3, SM4 and AVX-VNNI-INT16.

This patch set is for advertising these CPUIDs to userspace so that guests
can query them directly. Since these new instructions can't be intercepted
and only use xmm, ymm registers, host doesn't require to do additional
enabling for guest.

These new instructions are already updated into SDM [1].

---
[1] https://cdrdv2.intel.com/v1/dl/getContent/671200

Tao Su (4):
  x86: KVM: Advertise SHA512 CPUID to userspace
  x86: KVM: Advertise SM3 CPUID to userspace
  x86: KVM: Advertise SM4 CPUID to userspace
  KVM: x86: Advertise AVX-VNNI-INT16 CPUID to userspace

 arch/x86/include/asm/cpufeatures.h | 3 +++
 arch/x86/kvm/cpuid.c               | 8 ++++----
 arch/x86/kvm/reverse_cpuid.h       | 1 +
 3 files changed, 8 insertions(+), 4 deletions(-)


base-commit: 59b723cd2adbac2a34fc8e12c74ae26ae45bf230
-- 
2.34.1

[PATCH 1/4] x86: KVM: Advertise SHA512 CPUID to userspace

[Tao Su]

SHA512 is a new set of instructions in the latest Intel platform
Clearwater Forest, which contains VSHA512MSG1, VSHA512MSG2, VSHA512RNDS2.

SHA512 is enumerated via CPUID.(EAX=7,ECX=1):EAX[bit 0].

SHA512 is on an expected-dense CPUID leaf and some other bits on this leaf
have kernel usages. Considering SHA512 itself has not truly kernel usages,
hide this one in /proc/cpuinfo.

These instructions only operate in xmm, ymm registers and have no new VMX
controls, so there is no additional host enabling required for guests to
use these instructions, i.e. advertising SHA512 CPUID to userspace is
safe.

Tested-by: Jiaan Lu <jiaan.lu@intel.com>
Tested-by: Xuelian Guo <xuelian.guo@intel.com>
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
---
 arch/x86/include/asm/cpufeatures.h | 1 +
 arch/x86/kvm/cpuid.c               | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 913fd3a7bac6..896794528b81 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -317,6 +317,7 @@
 #define X86_FEATURE_ZEN1		(11*32+31) /* CPU based on Zen1 microarchitecture */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
+#define X86_FEATURE_SHA512		(12*32+ 0) /* SHA512 instructions */
 #define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* "avx_vnni" AVX VNNI instructions */
 #define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* "avx512_bf16" AVX512 BFLOAT16 instructions */
 #define X86_FEATURE_CMPCCXADD           (12*32+ 7) /* CMPccXADD instructions */
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 41786b834b16..5c7772567a4e 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -698,7 +698,7 @@ void kvm_set_cpu_caps(void)
 		kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD);
 
 	kvm_cpu_cap_mask(CPUID_7_1_EAX,
-		F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) |
+		F(SHA512) | F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) |
 		F(FZRM) | F(FSRS) | F(FSRC) |
 		F(AMX_FP16) | F(AVX_IFMA) | F(LAM)
 	);
-- 
2.34.1

[PATCH 2/4] x86: KVM: Advertise SM3 CPUID to userspace

[Tao Su]

SM3 is a new set of instructions in the latest Intel platform Clearwater
Forest, which contains VSM3MSG1, VSM3MSG2, VSM3RNDS2.

SM3 is enumerated via CPUID.(EAX=7,ECX=1):EAX[bit 1].

SM3 is on an expected-dense CPUID leaf and some other bits on this leaf
have kernel usages. Considering SM3 itself has no truly kernel usages,
hide this one in /proc/cpuinfo.

These instructions only operate in xmm registers and have no new VMX
controls, so there is no additional host enabling required for guests to
use these instructions, i.e. advertising SM3 CPUID to userspace is safe.

Tested-by: Jiaan Lu <jiaan.lu@intel.com>
Tested-by: Xuelian Guo <xuelian.guo@intel.com>
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
---
 arch/x86/include/asm/cpufeatures.h | 1 +
 arch/x86/kvm/cpuid.c               | 4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 896794528b81..460f4f93b039 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -318,6 +318,7 @@
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
 #define X86_FEATURE_SHA512		(12*32+ 0) /* SHA512 instructions */
+#define X86_FEATURE_SM3			(12*32+ 1) /* SM3 instructions */
 #define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* "avx_vnni" AVX VNNI instructions */
 #define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* "avx512_bf16" AVX512 BFLOAT16 instructions */
 #define X86_FEATURE_CMPCCXADD           (12*32+ 7) /* CMPccXADD instructions */
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 5c7772567a4e..e9f7489ba569 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -698,8 +698,8 @@ void kvm_set_cpu_caps(void)
 		kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD);
 
 	kvm_cpu_cap_mask(CPUID_7_1_EAX,
-		F(SHA512) | F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) |
-		F(FZRM) | F(FSRS) | F(FSRC) |
+		F(SHA512) | F(SM3) | F(AVX_VNNI) | F(AVX512_BF16) |
+		F(CMPCCXADD) | F(FZRM) | F(FSRS) | F(FSRC) |
 		F(AMX_FP16) | F(AVX_IFMA) | F(LAM)
 	);
 
-- 
2.34.1

Re: [PATCH 2/4] x86: KVM: Advertise SM3 CPUID to userspace

[Dave Hansen]

On 11/3/24 22:35, Tao Su wrote:
> SM3 is enumerated via CPUID.(EAX=7,ECX=1):EAX[bit 1].

Please don't put things like this in the changelog.  They're just a near
literal copy of what the code says and don't need to be duplicated.

Re: [PATCH 2/4] x86: KVM: Advertise SM3 CPUID to userspace

[Tao Su]

On Mon, Nov 04, 2024 at 08:40:57AM -0800, Dave Hansen wrote:
> On 11/3/24 22:35, Tao Su wrote:
> > SM3 is enumerated via CPUID.(EAX=7,ECX=1):EAX[bit 1].
> 
> Please don't put things like this in the changelog.  They're just a near
> literal copy of what the code says and don't need to be duplicated.

Yes, I will drop them. Thanks!

[PATCH 3/4] x86: KVM: Advertise SM4 CPUID to userspace

[Tao Su]

SM4 is a new set of instructions in the latest Intel platform
Clearwater Forest, which contains VSM4KEY4, VSM4RNDS4.

SM4 is enumerated via CPUID.(EAX=7,ECX=1):EAX[bit 2].

SM4 is on an expected-dense CPUID leaf and some other bits on this leaf
have kernel usages. Considering SM4 itself has no truly kernel usages,
hide this one in /proc/cpuinfo.

These instructions only operate in xmm, ymm registers and have no new VMX
controls, so there is no additional host enabling required for guests to
use these instructions, i.e. advertising SM4 CPUID to userspace is safe.

Tested-by: Jiaan Lu <jiaan.lu@intel.com>
Tested-by: Xuelian Guo <xuelian.guo@intel.com>
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
---
 arch/x86/include/asm/cpufeatures.h | 1 +
 arch/x86/kvm/cpuid.c               | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 460f4f93b039..d96277dceabf 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -319,6 +319,7 @@
 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
 #define X86_FEATURE_SHA512		(12*32+ 0) /* SHA512 instructions */
 #define X86_FEATURE_SM3			(12*32+ 1) /* SM3 instructions */
+#define X86_FEATURE_SM4			(12*32+ 2) /* SM4 instructions */
 #define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* "avx_vnni" AVX VNNI instructions */
 #define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* "avx512_bf16" AVX512 BFLOAT16 instructions */
 #define X86_FEATURE_CMPCCXADD           (12*32+ 7) /* CMPccXADD instructions */
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index e9f7489ba569..160b060121b2 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -698,7 +698,7 @@ void kvm_set_cpu_caps(void)
 		kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD);
 
 	kvm_cpu_cap_mask(CPUID_7_1_EAX,
-		F(SHA512) | F(SM3) | F(AVX_VNNI) | F(AVX512_BF16) |
+		F(SHA512) | F(SM3) | F(SM4) | F(AVX_VNNI) | F(AVX512_BF16) |
 		F(CMPCCXADD) | F(FZRM) | F(FSRS) | F(FSRC) |
 		F(AMX_FP16) | F(AVX_IFMA) | F(LAM)
 	);
-- 
2.34.1

[PATCH 4/4] KVM: x86: Advertise AVX-VNNI-INT16 CPUID to userspace

[Tao Su]

AVX-VNNI-INT16 is a new set of instructions in the latest Intel platform
Clearwater Forest, which can multiply and add unsigned and signed words
with and without saturation.

AVX-VNNI-INT16 is enumerated via CPUID.(EAX=7,ECX=1):EDX[bit 10].

Advertise AVX-VNNI-INT16 if it's supported in hardware. There are no new
VMX controls for the feature, i.e. the instructions can't be intercepted
and only use xmm, ymm registers.

Tested-by: Jiaan Lu <jiaan.lu@intel.com>
Tested-by: Xuelian Guo <xuelian.guo@intel.com>
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
---
 arch/x86/kvm/cpuid.c         | 4 ++--
 arch/x86/kvm/reverse_cpuid.h | 1 +
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 160b060121b2..68cde739a5a3 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -704,8 +704,8 @@ void kvm_set_cpu_caps(void)
 	);
 
 	kvm_cpu_cap_init_kvm_defined(CPUID_7_1_EDX,
-		F(AVX_VNNI_INT8) | F(AVX_NE_CONVERT) | F(PREFETCHITI) |
-		F(AMX_COMPLEX) | F(AVX10)
+		F(AVX_VNNI_INT8) | F(AVX_NE_CONVERT) | F(AMX_COMPLEX) |
+		F(AVX_VNNI_INT16) | F(PREFETCHITI) | F(AVX10)
 	);
 
 	kvm_cpu_cap_init_kvm_defined(CPUID_7_2_EDX,
diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h
index 0d17d6b70639..e46220ece83c 100644
--- a/arch/x86/kvm/reverse_cpuid.h
+++ b/arch/x86/kvm/reverse_cpuid.h
@@ -46,6 +46,7 @@ enum kvm_only_cpuid_leafs {
 #define X86_FEATURE_AVX_VNNI_INT8       KVM_X86_FEATURE(CPUID_7_1_EDX, 4)
 #define X86_FEATURE_AVX_NE_CONVERT      KVM_X86_FEATURE(CPUID_7_1_EDX, 5)
 #define X86_FEATURE_AMX_COMPLEX         KVM_X86_FEATURE(CPUID_7_1_EDX, 8)
+#define X86_FEATURE_AVX_VNNI_INT16      KVM_X86_FEATURE(CPUID_7_1_EDX, 10)
 #define X86_FEATURE_PREFETCHITI         KVM_X86_FEATURE(CPUID_7_1_EDX, 14)
 #define X86_FEATURE_AVX10               KVM_X86_FEATURE(CPUID_7_1_EDX, 19)
 
-- 
2.34.1

Re: [PATCH 0/4] Advertise CPUID for new instructions in Clearwater Forest

[Borislav Petkov]

On Mon, Nov 04, 2024 at 02:35:55PM +0800, Tao Su wrote:
> Latest Intel platform Clearwater Forest has introduced new instructions
> for SHA512, SM3, SM4 and AVX-VNNI-INT16.
> 
> This patch set is for advertising these CPUIDs to userspace so that guests
> can query them directly. Since these new instructions can't be intercepted
> and only use xmm, ymm registers, host doesn't require to do additional
> enabling for guest.
> 
> These new instructions are already updated into SDM [1].
> 
> ---
> [1] https://cdrdv2.intel.com/v1/dl/getContent/671200

I'm willing to bet some money that this URL will become invalid in a while.

> Tao Su (4):
>   x86: KVM: Advertise SHA512 CPUID to userspace
>   x86: KVM: Advertise SM3 CPUID to userspace
>   x86: KVM: Advertise SM4 CPUID to userspace
>   KVM: x86: Advertise AVX-VNNI-INT16 CPUID to userspace

Why aren't those a single patch instead of 4 very similar ones?

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Re: [PATCH 0/4] Advertise CPUID for new instructions in Clearwater Forest

[Tao Su]

On Mon, Nov 04, 2024 at 07:51:47AM +0100, Borislav Petkov wrote:
> On Mon, Nov 04, 2024 at 02:35:55PM +0800, Tao Su wrote:
> > Latest Intel platform Clearwater Forest has introduced new instructions
> > for SHA512, SM3, SM4 and AVX-VNNI-INT16.
> > 
> > This patch set is for advertising these CPUIDs to userspace so that guests
> > can query them directly. Since these new instructions can't be intercepted
> > and only use xmm, ymm registers, host doesn't require to do additional
> > enabling for guest.
> > 
> > These new instructions are already updated into SDM [1].
> > 
> > ---
> > [1] https://cdrdv2.intel.com/v1/dl/getContent/671200
> 
> I'm willing to bet some money that this URL will become invalid in a while.
> 

Thanks for such a quick review. Yes, the link may be invalid.

Would it be better if I attach rev, chapter and section?

> > Tao Su (4):
> >   x86: KVM: Advertise SHA512 CPUID to userspace
> >   x86: KVM: Advertise SM3 CPUID to userspace
> >   x86: KVM: Advertise SM4 CPUID to userspace
> >   KVM: x86: Advertise AVX-VNNI-INT16 CPUID to userspace
> 
> Why aren't those a single patch instead of 4 very similar ones?
> 

I mainly referred to the previous patch set [*] which is very similar to
this one. If you think a patch is better, I can send a v2 with only one
patch.

[*] https://lore.kernel.org/all/20221125125845.1182922-1-jiaxi.chen@linux.intel.com/

Re: [PATCH 0/4] Advertise CPUID for new instructions in Clearwater Forest

[Borislav Petkov]

On Mon, Nov 04, 2024 at 03:04:41PM +0800, Tao Su wrote:
> Would it be better if I attach rev, chapter and section?

Put enough information from the document so that one can find it doing a web
search. So that even if the vendor URL changes, a search engine will index it
shortly after again.

> I mainly referred to the previous patch set [*] which is very similar to
> this one.

That patch set is doing more than just adding bits although I still would've
merged patches 3-8 as they're simply adding feature bits and are obvious.

> If you think a patch is better, I can send a v2 with only one
> patch.

Yes please.

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Re: [PATCH 0/4] Advertise CPUID for new instructions in Clearwater Forest

[Tao Su]

On Mon, Nov 04, 2024 at 10:58:34AM +0100, Borislav Petkov wrote:
> On Mon, Nov 04, 2024 at 03:04:41PM +0800, Tao Su wrote:
> > Would it be better if I attach rev, chapter and section?
> 
> Put enough information from the document so that one can find it doing a web
> search. So that even if the vendor URL changes, a search engine will index it
> shortly after again.
> 

Sure, I agree with you.

> > I mainly referred to the previous patch set [*] which is very similar to
> > this one.
> 
> That patch set is doing more than just adding bits although I still would've
> merged patches 3-8 as they're simply adding feature bits and are obvious.
> 

Got it.

> > If you think a patch is better, I can send a v2 with only one
> > patch.
> 
> Yes please.

Will do, thanks!