From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4EF3721E098; Tue, 30 Jun 2026 02:16:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782785781; cv=none; b=R2mtrXu5U7V6isrPht0xsoXtyUamPReI6UskYIPU5X3kyvkx9ciFJdNklU7duu/AVA5x/DCy6IMNBow2oJuwC48V/jEEkVcioFitTfGLuPWxRCO0FTrVDeodY/cQ+J3dOHoHaWa7NFzeiT6SbgjbfEuutl9gKEOVNmxAYh6GUvk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782785781; c=relaxed/simple; bh=U78Ro3EdlnJE7s16xSYsFPIcwhK/8B3EB3JRXbiBJ/c=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=Uihd3X+l1RcqUXTflsYm0zpT2DFeEGkwSqNS+VeGByHBZ1keQOroo2nj7HNRZmivQz4KoY5INebzJ+VWxSLwACBHJ5vGbsUH8/qx154nCTtDVGJCLZwdt+VO8ILde5b5+5BDHvoyWCjvJNhbo4XjSrPjW82Oc1/BVl+jf7mlKT4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=c5kXUMfi; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="c5kXUMfi" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1782785780; x=1814321780; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=U78Ro3EdlnJE7s16xSYsFPIcwhK/8B3EB3JRXbiBJ/c=; b=c5kXUMfi54eNyfDg2c2HptH6DeLL2HwMeem9/jrbJ5Ha/H/CXJNQ7I0A YpeazFzXXTNcHdTYdv7zaRTajTQNOKnK+7RenEt307cP/YmM/V/I4vzRL OcXh/x5iDxOcR8mV0NIB6mxubRfokapj3ny7eM+QpyLCEMHRrsIXTq6qG UKAPm6XmQ5KVP+XPaj9LyiMr1oCwTAulO48TS35n+06fw+xYNZ+hmIJG9 j+Sz9Xpcj/gX3FpPDSkicctVv+zuNVHlz5fzo2fjm8jLwqdV0Hj+l2d7B llQ2z9CrcNK4Gsvt2QLNnJOna9xrE6Byrj+c7q19CnJLXOcJ87DRLO1tm A==; X-CSE-ConnectionGUID: Khcyj4NTSFa++OfAytClNA== X-CSE-MsgGUID: Q66V0VajQTWxl8JyVEhUdg== X-IronPort-AV: E=McAfee;i="6800,10657,11832"; a="83577301" X-IronPort-AV: E=Sophos;i="6.24,233,1774335600"; d="scan'208";a="83577301" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2026 19:16:19 -0700 X-CSE-ConnectionGUID: zTgDRPXQQV6LiMTwjIFMkQ== X-CSE-MsgGUID: UUKZV+H/SE6wedeX9ym/kg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,233,1774335600"; d="scan'208";a="282192576" Received: from dapengmi-mobl1.ccr.corp.intel.com (HELO [10.124.232.65]) ([10.124.232.65]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2026 19:16:17 -0700 Message-ID: Date: Tue, 30 Jun 2026 10:16:14 +0800 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 2/8] KVM: x86/pmu: Support Intel fixed counter 3 on mediated vPMU To: Zide Chen , Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Das Sandipan , Shukla Manali , Falcon Thomas , Xudong Hao References: <20260629231938.15129-1-zide.chen@intel.com> <20260629231938.15129-3-zide.chen@intel.com> Content-Language: en-US From: "Mi, Dapeng" In-Reply-To: <20260629231938.15129-3-zide.chen@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Reviewed-by: Dapeng Mi On 6/30/2026 7:19 AM, Zide Chen wrote: > From: Dapeng Mi > > Starting with Ice Lake, Intel introduced fixed counter 3, which counts > TOPDOWN.SLOTS - the number of available slots for an unhalted logical > processor. It serves as the denominator for top-level metrics in the > Top-down Microarchitecture Analysis method. > > Emulating this counter on legacy vPMU would require introducing a new > generic perf encoding for the Intel-specific TOPDOWN.SLOTS event in > order to call perf_get_hw_event_config(). This is undesirable as it > would pollute the generic perf event encoding. > > Moreover, KVM does not intend to emulate IA32_PERF_METRICS in the > legacy vPMU model, and without IA32_PERF_METRICS, emulating this > counter has little practical value. Therefore, expose fixed counter > 3 to guests only when mediated vPMU is enabled. > > Signed-off-by: Dapeng Mi > Co-developed-by: Zide Chen > Signed-off-by: Zide Chen > --- > v6: > - Update comments to replace 2 with KVM_MAX_NR_INTEL_FIXED_COUNTERS - 1. > v3: > - Move the non-contiguous counter filter code to pmu.c > v2: > - Don't advertise fixed counter 3 to userspace if the host doesn't > support it. > --- > arch/x86/include/asm/kvm_host.h | 2 +- > arch/x86/kvm/msrs.c | 4 ++-- > arch/x86/kvm/pmu.c | 18 +++++++++++++++++- > 3 files changed, 20 insertions(+), 4 deletions(-) > > diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h > index d8700eb848b4..dc9e4e8bfc07 100644 > --- a/arch/x86/include/asm/kvm_host.h > +++ b/arch/x86/include/asm/kvm_host.h > @@ -609,7 +609,7 @@ struct kvm_pmc { > #define KVM_MAX_NR_GP_COUNTERS KVM_MAX(KVM_MAX_NR_INTEL_GP_COUNTERS, \ > KVM_MAX_NR_AMD_GP_COUNTERS) > > -#define KVM_MAX_NR_INTEL_FIXED_COUNTERS 3 > +#define KVM_MAX_NR_INTEL_FIXED_COUNTERS 4 > #define KVM_MAX_NR_AMD_FIXED_COUNTERS 0 > #define KVM_MAX_NR_FIXED_COUNTERS KVM_MAX(KVM_MAX_NR_INTEL_FIXED_COUNTERS, \ > KVM_MAX_NR_AMD_FIXED_COUNTERS) > diff --git a/arch/x86/kvm/msrs.c b/arch/x86/kvm/msrs.c > index c230b18d87e3..3bf42d90ad14 100644 > --- a/arch/x86/kvm/msrs.c > +++ b/arch/x86/kvm/msrs.c > @@ -228,7 +228,7 @@ static const u32 msrs_to_save_base[] = { > > static const u32 msrs_to_save_pmu[] = { > MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, > - MSR_ARCH_PERFMON_FIXED_CTR0 + 2, > + MSR_ARCH_PERFMON_FIXED_CTR2, MSR_ARCH_PERFMON_FIXED_CTR3, > MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, > MSR_CORE_PERF_GLOBAL_CTRL, > MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG, > @@ -2688,7 +2688,7 @@ void kvm_init_msr_lists(void) > { > unsigned i; > > - BUILD_BUG_ON_MSG(KVM_MAX_NR_FIXED_COUNTERS != 3, > + BUILD_BUG_ON_MSG(KVM_MAX_NR_FIXED_COUNTERS != 4, > "Please update the fixed PMCs in msrs_to_save_pmu[]"); > > num_msrs_to_save = 0; > diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c > index 62d0ed99ebe9..f82ba63767d0 100644 > --- a/arch/x86/kvm/pmu.c > +++ b/arch/x86/kvm/pmu.c > @@ -99,7 +99,8 @@ static const struct x86_cpu_id vmx_pebs_pdist_cpu[] = { > * all perf counters (both gp and fixed). The mapping relationship > * between pmc and perf counters is as the following: > * * Intel: [0 .. KVM_MAX_NR_INTEL_GP_COUNTERS-1] <=> gp counters > - * [KVM_FIXED_PMC_BASE_IDX .. KVM_FIXED_PMC_BASE_IDX + 2] <=> fixed > + * [KVM_FIXED_PMC_BASE_IDX .. KVM_FIXED_PMC_BASE_IDX + > + * KVM_MAX_NR_INTEL_FIXED_COUNTERS - 1] <=> fixed > * * AMD: [0 .. AMD64_NUM_COUNTERS-1] and, for families 15H > * and later, [0 .. AMD64_NUM_COUNTERS_CORE-1] <=> gp counters > */ > @@ -134,6 +135,8 @@ void kvm_init_pmu_capability(struct kvm_pmu_ops *pmu_ops) > { > bool is_intel = boot_cpu_data.x86_vendor == X86_VENDOR_INTEL; > int min_nr_gp_ctrs = pmu_ops->MIN_NR_GP_COUNTERS; > + union cpuid10_edx edx; > + u32 eax, ebx, ecx; > > /* > * Hybrid PMUs don't play nice with virtualization without careful > @@ -181,6 +184,19 @@ void kvm_init_pmu_capability(struct kvm_pmu_ops *pmu_ops) > kvm_pmu_cap.num_counters_fixed = min(kvm_pmu_cap.num_counters_fixed, > KVM_MAX_NR_FIXED_COUNTERS); > > + /* > + * Currently, KVM doesn't support non-contiguous fixed counters; make > + * sure only contiguous ones are retained in kvm_pmu_cap. > + */ > + if (kvm_host_pmu.version >= 5) { > + cpuid(0xa, &eax, &ebx, &ecx, &edx.full); > + if (kvm_pmu_cap.num_counters_fixed > edx.split.num_counters_fixed) > + kvm_pmu_cap.num_counters_fixed = edx.split.num_counters_fixed; > + } > + > + if (!enable_mediated_pmu && kvm_pmu_cap.num_counters_fixed > 3) > + kvm_pmu_cap.num_counters_fixed = 3; > + > kvm_pmu_eventsel.INSTRUCTIONS_RETIRED = > perf_get_hw_event_config(PERF_COUNT_HW_INSTRUCTIONS); > kvm_pmu_eventsel.BRANCH_INSTRUCTIONS_RETIRED =