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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6e254814029sm61998046d6.29.2025.02.04.04.55.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 04 Feb 2025 04:55:08 -0800 (PST) Message-ID: Date: Tue, 4 Feb 2025 13:55:01 +0100 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Reply-To: eric.auger@redhat.com Subject: Re: [PATCH RFCv2 00/13] iommu: Add MSI mapping support with nested SMMU Content-Language: en-US To: Jason Gunthorpe Cc: Shameerali Kolothum Thodi , Nicolin Chen , "will@kernel.org" , "robin.murphy@arm.com" , "kevin.tian@intel.com" , "tglx@linutronix.de" , "maz@kernel.org" , "alex.williamson@redhat.com" , "joro@8bytes.org" , "shuah@kernel.org" , "reinette.chatre@intel.com" , "yebin (H)" , "apatel@ventanamicro.com" , "shivamurthy.shastri@linutronix.de" , "bhelgaas@google.com" , "anna-maria@linutronix.de" , "yury.norov@gmail.com" , "nipun.gupta@amd.com" , "iommu@lists.linux.dev" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "kvm@vger.kernel.org" , "linux-kselftest@vger.kernel.org" , "patches@lists.linux.dev" , "jean-philippe@linaro.org" , "mdf@kernel.org" , "mshavit@google.com" , "smostafa@google.com" , "ddutile@redhat.com" References: <4946ea266bdc4b1e8796dee1b228bd8f@huawei.com> <20250123132432.GJ5556@nvidia.com> <20250129150454.GH5556@nvidia.com> <8e4c21b5-3b79-4f0b-b920-59b825c2fb81@redhat.com> <20250129201307.GJ5556@nvidia.com> From: Eric Auger In-Reply-To: <20250129201307.GJ5556@nvidia.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi Jason, On 1/29/25 9:13 PM, Jason Gunthorpe wrote: > On Wed, Jan 29, 2025 at 06:46:20PM +0100, Eric Auger wrote: >>>>> This missing peice is cleaning up the ITS mapping to allow for >>>>> multiple ITS pages. I've imagined that kvm would someone give iommufd >>>>> a FD that holds the specific ITS pages instead of the >>>>> IOMMU_OPTION_SW_MSI_START/SIZE flow. >>>> That's what I don't get: at the moment you only pass the gIOVA. With >>>> technique 2, how can you build the nested mapping, ie. >>>> >>>> S1 S2 >>>> gIOVA -> gDB -> hDB >>>> >>>> without passing the full gIOVA/gDB S1 mapping to the host? >>> The nested S2 mapping is already setup before the VM boots: >>> >>> - The VMM puts the ITS page (hDB) into the S2 at a fixed address (gDB) >> Ah OK. Your gDB has nothing to do with the actual S1 guest gDB, >> right? > I'm not totally sure what you mean by gDB? The above diagram suggests > it is the ITS page address in the S2? Ie the guest physical address of > the ITS. Yes this is what I meant, ie. the guest ITS doorbell GPA > > Within the VM, when it goes to call iommu_dma_prepare_msi(), it will > provide the gDB adress as the phys_addr_t msi_addr. > > This happens because the GIC driver will have been informed of the ITS > page at the gDB address, and it will use > iommu_dma_prepare_msi(). Exactly the same as bare metal. understood this is the standard MSI binding scheme. > >> It is computed in iommufd_sw_msi_get_map() from the sw_msi_start pool. >> Is that correct? > Yes, for a single ITS page it will reliably be put at sw_msi_start. > Since the VMM can provide sw_msi_start through the OPTION, the VMM can > place the ITS page where it wants and then program the ACPI to tell > the VM to call iommu_dma_prepare_msi(). (don't use this flow, it > doesn't work for multi ITS, for testing only) OK so you need to set host sw_msi_start to the guest doorbell GPA which is currently set, in qemu, at GITS_TRANSLATER 0x08080000 + 0x10000 In my original integration, I passed pairs of S1 gIOVA/gDB used by the guest and this gDB was directly reused for mapping hDB. I think I get it now. Eric > >> https://lore.kernel.org/all/20210411111228.14386-9-eric.auger@redhat.com/ >> I was passing both the gIOVA and the "true" gDB Eric > If I understand this right, it still had the hypervisor dynamically > setting up the S2, here it is pre-set and static? > > Jason >