Re: [PATCH 1/2] x86/mce: Fix missing address mask in recovery for errors in TDX/SEAM non-root mode

["Huang, Kai" <kai.huang@intel.com>]

On Wed, 2025-06-18 at 23:39 +0000, Luck, Tony wrote:
> > > Commit 8a01ec97dc066 ("x86/mce: Mask out non-address bits from machine
> > > check bank") introduced a new #define MCI_ADDR_PHYSADDR for the mask of
> > > valid physical address bits within the machine check bank address register.
> > > 
> > > This is particularly needed in the case of errors in TDX/SEAM non-root mode
> > > because the reported address contains the TDX KeyID.
> > > 
> > 
> > Just wondering, do you know whether this is documented anywhere?  If it is,
> > I think it should be helpful if you can refer that in the changelog.
> 
> It's sort of hinted at in the SDM Vol 3B Figure 17-7. IA32_MCi_ADDR MSR
> with the footnote in the diagram:
> 
>   "Useful bits in this field depend on the address methodology in use when the
>    the register state is saved."

Thanks for the info.

> 
> Maybe there is something more explicit in documentation for memory encryption?

I didn't find any.  The TDX module base architecture spec (16.2.3. Memory
Integrity Error Logging, Machine Checks and Unbreakable Shutdowns) says
below:

  The poison memory address, at a granularity no finer than 32 bytes, is
  logged in IA32_MCi_ADDRESS MSRs.

It doesn't explicitly say KeyID is appended.