From mboxrd@z Thu Jan 1 00:00:00 1970 From: Junaid Shahid Subject: [PATCH 0/4] Lockless Access Tracking for Intel CPUs without EPT A bits Date: Wed, 26 Oct 2016 19:19:41 -0700 Message-ID: Cc: pbonzini@redhat.com, andreslc@google.com, pfeiner@google.com To: kvm@vger.kernel.org Return-path: Received: from mail-pf0-f181.google.com ([209.85.192.181]:35956 "EHLO mail-pf0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932239AbcJ0CTs (ORCPT ); Wed, 26 Oct 2016 22:19:48 -0400 Received: by mail-pf0-f181.google.com with SMTP id e6so7253055pfk.3 for ; Wed, 26 Oct 2016 19:19:48 -0700 (PDT) Sender: kvm-owner@vger.kernel.org List-ID: Hi, This patch series implements a lockless access tracking mechanism for KVM when running on Intel CPUs that do not have EPT A/D bits. Currently, KVM tracks accesses on these machines by just clearing the PTEs and then remapping them when they are accessed again. However, the remapping requires acquiring the MMU lock in order to lookup the information needed to construct the PTE. On high core count VMs, this can result in significant MMU lock contention when running some memory-intesive workloads. This new mechanism just marks the PTEs as not-present, but keeps all the information within the PTE instead of clearing it. When the page is accessed again, the PTE can thus be restored without needing to acquire the MMU lock. Junaid Shahid (4): kvm: x86: mmu: Use symbolic constants for EPT Violation Exit Qualifications kvm: x86: mmu: Rename spte_is_locklessly_modifiable() kvm: x86: mmu: Fast Page Fault path retries kvm: x86: mmu: Lockless access tracking for Intel CPUs without EPT A bits. arch/x86/include/asm/vmx.h | 55 +++++++ arch/x86/kvm/mmu.c | 399 +++++++++++++++++++++++++++++++++------------ arch/x86/kvm/mmu.h | 2 + arch/x86/kvm/vmx.c | 40 ++++- 4 files changed, 382 insertions(+), 114 deletions(-) -- 2.8.0.rc3.226.g39d4020