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Sat, 09 May 2026 06:10:14 -0700 (PDT) From: Zhanpeng Zhang To: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Conor Dooley , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Himanshu Chauhan , Will Deacon , Mark Rutland , Atish Patra , Anup Patel , Shuah Khan , Yunhui Cui , Zhu Yuan , Zhanpeng Zhang Subject: [PATCH v9 0/5] riscv: add SBI Supervisor Software Events support Date: Sat, 9 May 2026 21:09:57 +0800 Message-ID: X-Mailer: git-send-email 2.50.1 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This series continues Clément's SBI Supervisor Software Events (SSE) Linux support. Most of the framework is still Clément's work; many thanks to him for bringing the series this far. Clément reached out and suggested that I could continue the upstream work, so I am picking up the series from here. SSE gives the SBI a firmware-to-S/HS-mode event delivery path that does not depend on ordinary S-mode interrupt delivery. This is useful for NMI-style platform events and for PMU overflow delivery through firmware. This respin mainly fixes two issues: - KVM Context Corruption An SSE can interrupt HS-mode code around guest execution, run a synthetic SSE handler, and then complete back through firmware. The handler episode must be transparent to Linux-owned trap and virtualization state. This version folds the stvec and hstatus preservation into the Linux SSE entry wrapper, rather than relying on OpenSBI to keep extra hidden resume state. This follows the earlier discussion [1]. - SSE Handler's SSTATUS Leakage With CONFIG_RISCV_PMU_SBI_SSE, perf can use the local PMU overflow SSE event instead of the ordinary PMU interrupt. This makes the PMU overflow handler a real hot path for SSE: workloads such as "perf top" can enter the SSE handler and completion paths at a high rate. The previous code did not preserve the interrupted sstatus.SIE/SPIE/SPP state separately from the synthetic handler trap-return state, so high-frequency PMU-SSE delivery could quickly expose the leakage. One observed failure mode was an "environment call from U-mode" panic. This series addresses that by making the SSE entry wrapper preserve the live sstatus state around the handler before completing the event. The selftest has also been extended to cover the high-frequency PMU-SSE patterns that exposed these bugs. The new stress modes exercise repeated handler entry and completion, SBI calls from a handler, PMU stop/start activity, and re-injection. How to test: Build a kernel with at least: CONFIG_RISCV_SBI_SSE=y CONFIG_RISCV_PMU_SBI=y CONFIG_RISCV_PMU_SBI_SSE=y Build the selftest module against that kernel and run the smoke test: ./run_sse_test.sh Then run the stress layers. Use stress=1 to run them after the smoke test, or stress=2 to run only the stress layers: ./run_sse_test.sh stress={0,1,2} Known limitations and follow-up work: SSE is a relatively large extension which builds synthetic supervisor contexts and then resumes the interrupted context through firmware. This series fixes the issues found so far in that entry/completion path, but I think it still needs more testing and review. There may still be corner cases in the constructed handler context or in the state restored after completion that this series does not cover yet. The next planned area is virtualization support. Follow-up work is expected to distinguish host and guest PMU-SSE samples, and to support delivering SSE events to guests, i.e. the KVM-SSE work from earlier revisions. [1] https://lore.kernel.org/r/9290f53d-3545-4299-9781-c1c558f71158@rivosinc.com --- Changes in v9: - Picked up Clément's v8 series and rebased it onto the current RISC-V for-next branch. - Fixed KVM Context Corruption by keeping stvec and hstatus stable across the synthetic SSE handler episode. - Fixed SSE Handler's SSTATUS Leakage, where interrupted sstatus.SIE/SPIE/SPP state could be confused with the handler trap-return state under high-frequency PMU-SSE delivery. - Extended the SSE selftest with stress={0,1,2} modes that cover repeated handler entry, SBI calls, PMU activity and re-injection, and fixed event registration and attribute-buffer lifetime corner cases. - Updated MAINTAINERS for the RISC-V SSE driver. Previous versions: v8: https://lore.kernel.org/r/20251105082639.342973-1-cleger@rivosinc.com Clément Léger (5): riscv: add SBI SSE extension definitions riscv: add support for SBI Supervisor Software Events extension drivers: firmware: add riscv SSE support perf: RISC-V: add support for SSE event selftests/riscv: add SSE test module MAINTAINERS | 17 + arch/riscv/include/asm/asm.h | 14 +- arch/riscv/include/asm/sbi.h | 61 ++ arch/riscv/include/asm/scs.h | 7 + arch/riscv/include/asm/sse.h | 47 ++ arch/riscv/include/asm/switch_to.h | 14 + arch/riscv/include/asm/thread_info.h | 1 + arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/asm-offsets.c | 14 + arch/riscv/kernel/sbi_sse.c | 162 ++++ arch/riscv/kernel/sbi_sse_entry.S | 187 +++++ drivers/firmware/Kconfig | 1 + drivers/firmware/Makefile | 1 + drivers/firmware/riscv/Kconfig | 15 + drivers/firmware/riscv/Makefile | 3 + drivers/firmware/riscv/riscv_sbi_sse.c | 694 ++++++++++++++++ drivers/perf/Kconfig | 10 + drivers/perf/riscv_pmu.c | 23 + drivers/perf/riscv_pmu_sbi.c | 71 +- include/linux/perf/riscv_pmu.h | 5 + include/linux/riscv_sbi_sse.h | 57 ++ tools/testing/selftests/riscv/Makefile | 2 +- tools/testing/selftests/riscv/sse/Makefile | 5 + .../selftests/riscv/sse/module/Makefile | 16 + .../riscv/sse/module/riscv_sse_test.c | 769 ++++++++++++++++++ .../selftests/riscv/sse/run_sse_test.sh | 48 ++ 26 files changed, 2231 insertions(+), 14 deletions(-) create mode 100644 arch/riscv/include/asm/sse.h create mode 100644 arch/riscv/kernel/sbi_sse.c create mode 100644 arch/riscv/kernel/sbi_sse_entry.S create mode 100644 drivers/firmware/riscv/Kconfig create mode 100644 drivers/firmware/riscv/Makefile create mode 100644 drivers/firmware/riscv/riscv_sbi_sse.c create mode 100644 include/linux/riscv_sbi_sse.h create mode 100644 tools/testing/selftests/riscv/sse/Makefile create mode 100644 tools/testing/selftests/riscv/sse/module/Makefile create mode 100644 tools/testing/selftests/riscv/sse/module/riscv_sse_test.c create mode 100644 tools/testing/selftests/riscv/sse/run_sse_test.sh -- 2.50.1 (Apple Git-155)