* [PATCH v6 1/3] vfio/pci: Extract duplicated code into macro
2024-06-19 11:58 [PATCH v6 0/3] vfio/pci: Support 8-byte PCI loads and stores Gerd Bayer
@ 2024-06-19 11:58 ` Gerd Bayer
2024-06-19 11:58 ` [PATCH v6 2/3] vfio/pci: Support 8-byte PCI loads and stores Gerd Bayer
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Gerd Bayer @ 2024-06-19 11:58 UTC (permalink / raw)
To: Alex Williamson, Jason Gunthorpe, Niklas Schnelle, Ramesh Thomas
Cc: kvm, linux-s390, Ankit Agrawal, Yishai Hadas, Halil Pasic,
Ben Segal, Tian, Kevin, Julian Ruess, Gerd Bayer
vfio_pci_core_do_io_rw() repeats the same code for multiple access
widths. Factor this out into a macro
Suggested-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Gerd Bayer <gbayer@linux.ibm.com>
---
drivers/vfio/pci/vfio_pci_rdwr.c | 106 ++++++++++++++-----------------
1 file changed, 46 insertions(+), 60 deletions(-)
diff --git a/drivers/vfio/pci/vfio_pci_rdwr.c b/drivers/vfio/pci/vfio_pci_rdwr.c
index 03b8f7ada1ac..d07bfb0ab892 100644
--- a/drivers/vfio/pci/vfio_pci_rdwr.c
+++ b/drivers/vfio/pci/vfio_pci_rdwr.c
@@ -90,6 +90,40 @@ VFIO_IOREAD(8)
VFIO_IOREAD(16)
VFIO_IOREAD(32)
+#define VFIO_IORDWR(size) \
+static int vfio_pci_iordwr##size(struct vfio_pci_core_device *vdev,\
+ bool iswrite, bool test_mem, \
+ void __iomem *io, char __user *buf, \
+ loff_t off, size_t *filled) \
+{ \
+ u##size val; \
+ int ret; \
+ \
+ if (iswrite) { \
+ if (copy_from_user(&val, buf, sizeof(val))) \
+ return -EFAULT; \
+ \
+ ret = vfio_pci_core_iowrite##size(vdev, test_mem, \
+ val, io + off); \
+ if (ret) \
+ return ret; \
+ } else { \
+ ret = vfio_pci_core_ioread##size(vdev, test_mem, \
+ &val, io + off); \
+ if (ret) \
+ return ret; \
+ \
+ if (copy_to_user(buf, &val, sizeof(val))) \
+ return -EFAULT; \
+ } \
+ \
+ *filled = sizeof(val); \
+ return 0; \
+} \
+
+VFIO_IORDWR(8)
+VFIO_IORDWR(16)
+VFIO_IORDWR(32)
/*
* Read or write from an __iomem region (MMIO or I/O port) with an excluded
* range which is inaccessible. The excluded range drops writes and fills
@@ -115,71 +149,23 @@ ssize_t vfio_pci_core_do_io_rw(struct vfio_pci_core_device *vdev, bool test_mem,
fillable = 0;
if (fillable >= 4 && !(off % 4)) {
- u32 val;
-
- if (iswrite) {
- if (copy_from_user(&val, buf, 4))
- return -EFAULT;
-
- ret = vfio_pci_core_iowrite32(vdev, test_mem,
- val, io + off);
- if (ret)
- return ret;
- } else {
- ret = vfio_pci_core_ioread32(vdev, test_mem,
- &val, io + off);
- if (ret)
- return ret;
-
- if (copy_to_user(buf, &val, 4))
- return -EFAULT;
- }
+ ret = vfio_pci_iordwr32(vdev, iswrite, test_mem,
+ io, buf, off, &filled);
+ if (ret)
+ return ret;
- filled = 4;
} else if (fillable >= 2 && !(off % 2)) {
- u16 val;
-
- if (iswrite) {
- if (copy_from_user(&val, buf, 2))
- return -EFAULT;
-
- ret = vfio_pci_core_iowrite16(vdev, test_mem,
- val, io + off);
- if (ret)
- return ret;
- } else {
- ret = vfio_pci_core_ioread16(vdev, test_mem,
- &val, io + off);
- if (ret)
- return ret;
-
- if (copy_to_user(buf, &val, 2))
- return -EFAULT;
- }
+ ret = vfio_pci_iordwr16(vdev, iswrite, test_mem,
+ io, buf, off, &filled);
+ if (ret)
+ return ret;
- filled = 2;
} else if (fillable) {
- u8 val;
-
- if (iswrite) {
- if (copy_from_user(&val, buf, 1))
- return -EFAULT;
-
- ret = vfio_pci_core_iowrite8(vdev, test_mem,
- val, io + off);
- if (ret)
- return ret;
- } else {
- ret = vfio_pci_core_ioread8(vdev, test_mem,
- &val, io + off);
- if (ret)
- return ret;
-
- if (copy_to_user(buf, &val, 1))
- return -EFAULT;
- }
+ ret = vfio_pci_iordwr8(vdev, iswrite, test_mem,
+ io, buf, off, &filled);
+ if (ret)
+ return ret;
- filled = 1;
} else {
/* Fill reads with -1, drop writes */
filled = min(count, (size_t)(x_end - off));
--
2.45.2
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v6 2/3] vfio/pci: Support 8-byte PCI loads and stores
2024-06-19 11:58 [PATCH v6 0/3] vfio/pci: Support 8-byte PCI loads and stores Gerd Bayer
2024-06-19 11:58 ` [PATCH v6 1/3] vfio/pci: Extract duplicated code into macro Gerd Bayer
@ 2024-06-19 11:58 ` Gerd Bayer
2024-06-19 11:58 ` [PATCH v6 3/3] vfio/pci: Fix typo in macro to declare accessors Gerd Bayer
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Gerd Bayer @ 2024-06-19 11:58 UTC (permalink / raw)
To: Alex Williamson, Jason Gunthorpe, Niklas Schnelle, Ramesh Thomas
Cc: kvm, linux-s390, Ankit Agrawal, Yishai Hadas, Halil Pasic,
Ben Segal, Tian, Kevin, Julian Ruess, Gerd Bayer
From: Ben Segal <bpsegal@us.ibm.com>
Many PCI adapters can benefit or even require full 64bit read
and write access to their registers. In order to enable work on
user-space drivers for these devices add two new variations
vfio_pci_core_io{read|write}64 of the existing access methods
when the architecture supports 64-bit ioreads and iowrites.
Signed-off-by: Ben Segal <bpsegal@us.ibm.com>
Co-developed-by: Gerd Bayer <gbayer@linux.ibm.com>
Signed-off-by: Gerd Bayer <gbayer@linux.ibm.com>
---
drivers/vfio/pci/vfio_pci_rdwr.c | 16 ++++++++++++++++
include/linux/vfio_pci_core.h | 3 +++
2 files changed, 19 insertions(+)
diff --git a/drivers/vfio/pci/vfio_pci_rdwr.c b/drivers/vfio/pci/vfio_pci_rdwr.c
index d07bfb0ab892..66b72c289284 100644
--- a/drivers/vfio/pci/vfio_pci_rdwr.c
+++ b/drivers/vfio/pci/vfio_pci_rdwr.c
@@ -89,6 +89,9 @@ EXPORT_SYMBOL_GPL(vfio_pci_core_ioread##size);
VFIO_IOREAD(8)
VFIO_IOREAD(16)
VFIO_IOREAD(32)
+#ifdef ioread64
+VFIO_IOREAD(64)
+#endif
#define VFIO_IORDWR(size) \
static int vfio_pci_iordwr##size(struct vfio_pci_core_device *vdev,\
@@ -124,6 +127,10 @@ static int vfio_pci_iordwr##size(struct vfio_pci_core_device *vdev,\
VFIO_IORDWR(8)
VFIO_IORDWR(16)
VFIO_IORDWR(32)
+#if defined(ioread64) && defined(iowrite64)
+VFIO_IORDWR(64)
+#endif
+
/*
* Read or write from an __iomem region (MMIO or I/O port) with an excluded
* range which is inaccessible. The excluded range drops writes and fills
@@ -148,6 +155,15 @@ ssize_t vfio_pci_core_do_io_rw(struct vfio_pci_core_device *vdev, bool test_mem,
else
fillable = 0;
+#if defined(ioread64) && defined(iowrite64)
+ if (fillable >= 8 && !(off % 8)) {
+ ret = vfio_pci_iordwr64(vdev, iswrite, test_mem,
+ io, buf, off, &filled);
+ if (ret)
+ return ret;
+
+ } else
+#endif
if (fillable >= 4 && !(off % 4)) {
ret = vfio_pci_iordwr32(vdev, iswrite, test_mem,
io, buf, off, &filled);
diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h
index f87067438ed4..7b45f70f84c3 100644
--- a/include/linux/vfio_pci_core.h
+++ b/include/linux/vfio_pci_core.h
@@ -155,5 +155,8 @@ int vfio_pci_core_ioread##size(struct vfio_pci_core_device *vdev, \
VFIO_IOREAD_DECLATION(8)
VFIO_IOREAD_DECLATION(16)
VFIO_IOREAD_DECLATION(32)
+#ifdef ioread64
+VFIO_IOREAD_DECLATION(64)
+#endif
#endif /* VFIO_PCI_CORE_H */
--
2.45.2
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v6 3/3] vfio/pci: Fix typo in macro to declare accessors
2024-06-19 11:58 [PATCH v6 0/3] vfio/pci: Support 8-byte PCI loads and stores Gerd Bayer
2024-06-19 11:58 ` [PATCH v6 1/3] vfio/pci: Extract duplicated code into macro Gerd Bayer
2024-06-19 11:58 ` [PATCH v6 2/3] vfio/pci: Support 8-byte PCI loads and stores Gerd Bayer
@ 2024-06-19 11:58 ` Gerd Bayer
2024-06-21 20:17 ` [PATCH v6 0/3] vfio/pci: Support 8-byte PCI loads and stores Alex Williamson
2024-06-21 21:50 ` Ramesh Thomas
4 siblings, 0 replies; 7+ messages in thread
From: Gerd Bayer @ 2024-06-19 11:58 UTC (permalink / raw)
To: Alex Williamson, Jason Gunthorpe, Niklas Schnelle, Ramesh Thomas
Cc: kvm, linux-s390, Ankit Agrawal, Yishai Hadas, Halil Pasic,
Ben Segal, Tian, Kevin, Julian Ruess, Gerd Bayer
Correct spelling of DECLA[RA]TION
Suggested-by: Ramesh Thomas <ramesh.thomas@intel.com>
Signed-off-by: Gerd Bayer <gbayer@linux.ibm.com>
---
include/linux/vfio_pci_core.h | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h
index 7b45f70f84c3..fbb472dd99b3 100644
--- a/include/linux/vfio_pci_core.h
+++ b/include/linux/vfio_pci_core.h
@@ -137,26 +137,26 @@ bool vfio_pci_core_range_intersect_range(loff_t buf_start, size_t buf_cnt,
loff_t *buf_offset,
size_t *intersect_count,
size_t *register_offset);
-#define VFIO_IOWRITE_DECLATION(size) \
+#define VFIO_IOWRITE_DECLARATION(size) \
int vfio_pci_core_iowrite##size(struct vfio_pci_core_device *vdev, \
bool test_mem, u##size val, void __iomem *io);
-VFIO_IOWRITE_DECLATION(8)
-VFIO_IOWRITE_DECLATION(16)
-VFIO_IOWRITE_DECLATION(32)
+VFIO_IOWRITE_DECLARATION(8)
+VFIO_IOWRITE_DECLARATION(16)
+VFIO_IOWRITE_DECLARATION(32)
#ifdef iowrite64
-VFIO_IOWRITE_DECLATION(64)
+VFIO_IOWRITE_DECLARATION(64)
#endif
-#define VFIO_IOREAD_DECLATION(size) \
+#define VFIO_IOREAD_DECLARATION(size) \
int vfio_pci_core_ioread##size(struct vfio_pci_core_device *vdev, \
bool test_mem, u##size *val, void __iomem *io);
-VFIO_IOREAD_DECLATION(8)
-VFIO_IOREAD_DECLATION(16)
-VFIO_IOREAD_DECLATION(32)
+VFIO_IOREAD_DECLARATION(8)
+VFIO_IOREAD_DECLARATION(16)
+VFIO_IOREAD_DECLARATION(32)
#ifdef ioread64
-VFIO_IOREAD_DECLATION(64)
+VFIO_IOREAD_DECLARATION(64)
#endif
#endif /* VFIO_PCI_CORE_H */
--
2.45.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v6 0/3] vfio/pci: Support 8-byte PCI loads and stores
2024-06-19 11:58 [PATCH v6 0/3] vfio/pci: Support 8-byte PCI loads and stores Gerd Bayer
` (2 preceding siblings ...)
2024-06-19 11:58 ` [PATCH v6 3/3] vfio/pci: Fix typo in macro to declare accessors Gerd Bayer
@ 2024-06-21 20:17 ` Alex Williamson
2024-06-21 21:50 ` Ramesh Thomas
4 siblings, 0 replies; 7+ messages in thread
From: Alex Williamson @ 2024-06-21 20:17 UTC (permalink / raw)
To: Gerd Bayer
Cc: Jason Gunthorpe, Niklas Schnelle, Ramesh Thomas, kvm, linux-s390,
Ankit Agrawal, Yishai Hadas, Halil Pasic, Ben Segal, Tian, Kevin,
Julian Ruess
On Wed, 19 Jun 2024 13:58:44 +0200
Gerd Bayer <gbayer@linux.ibm.com> wrote:
> Hi all,
>
> this all started with a single patch by Ben to enable writing a user-mode
> driver for a PCI device that requires 64bit register read/writes on s390.
> A quick grep showed that there are several other drivers for PCI devices
> in the kernel that use readq/writeq and eventually could use this, too.
> So we decided to propose this for general inclusion.
>
> A couple of suggestions for refactorizations by Jason Gunthorpe and Alex
> Williamson later [1], I arrived at this little series that avoids some
> code duplication in vfio_pci_core_do_io_rw().
> Also, I've added a small patch to correct the spelling in one of the
> declaration macros that was suggested by Ramesh Thomas [2]. However,
> after some discussions about making 8-byte accesses available for x86,
> Ramesh and I decided to do this in a separate patch [3].
>
> This version was tested with a pass-through PCI device in a KVM guest
> and with explicit test reads of size 8, 16, 32, and 64 bit on s390.
> For 32bit architectures this has only been compile tested for the
> 32bit ARM architecture.
>
> Thank you,
> Gerd Bayer
>
>
> [1] https://lore.kernel.org/all/20240422153508.2355844-1-gbayer@linux.ibm.com/
> [2] https://lore.kernel.org/kvm/20240425165604.899447-1-gbayer@linux.ibm.com/T/#m1b51fe155c60d04313695fbee11a2ccea856a98c
> [3] https://lore.kernel.org/all/20240522232125.548643-1-ramesh.thomas@intel.com/
>
> Changes v5 -> v6:
> - restrict patch 3/3 to just the typo fix - no move of semicolons
Applied to vfio next branch for v6.11. Thanks,
Alex
>
> Changes v4 -> v5:
> - Make 8-byte accessors depend on the definitions of ioread64 and
> iowrite64, again. Ramesh agreed to sort these out for x86 separately.
>
> Changes v3 -> v4:
> - Make 64-bit accessors depend on CONFIG_64BIT (for x86, too).
> - Drop conversion of if-else if chain to switch-case.
> - Add patch to fix spelling of declaration macro.
>
> Changes v2 -> v3:
> - Introduce macro to generate body of different-size accesses in
> vfio_pci_core_do_io_rw (courtesy Alex Williamson).
> - Convert if-else if chain to a switch-case construct to better
> accommodate conditional compiles.
>
> Changes v1 -> v2:
> - On non 64bit architecture use at most 32bit accesses in
> vfio_pci_core_do_io_rw and describe that in the commit message.
> - Drop the run-time error on 32bit architectures.
> - The #endif splitting the "else if" is not really fortunate, but I'm
> open to suggestions.
>
>
> Ben Segal (1):
> vfio/pci: Support 8-byte PCI loads and stores
>
> Gerd Bayer (2):
> vfio/pci: Extract duplicated code into macro
> vfio/pci: Fix typo in macro to declare accessors
>
> drivers/vfio/pci/vfio_pci_rdwr.c | 122 ++++++++++++++++---------------
> include/linux/vfio_pci_core.h | 21 +++---
> 2 files changed, 74 insertions(+), 69 deletions(-)
>
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v6 0/3] vfio/pci: Support 8-byte PCI loads and stores
2024-06-19 11:58 [PATCH v6 0/3] vfio/pci: Support 8-byte PCI loads and stores Gerd Bayer
` (3 preceding siblings ...)
2024-06-21 20:17 ` [PATCH v6 0/3] vfio/pci: Support 8-byte PCI loads and stores Alex Williamson
@ 2024-06-21 21:50 ` Ramesh Thomas
2024-12-03 18:01 ` Ramesh Thomas
4 siblings, 1 reply; 7+ messages in thread
From: Ramesh Thomas @ 2024-06-21 21:50 UTC (permalink / raw)
To: Gerd Bayer, Alex Williamson, Jason Gunthorpe, Niklas Schnelle
Cc: kvm, linux-s390, Ankit Agrawal, Yishai Hadas, Halil Pasic,
Ben Segal, Tian, Kevin, Julian Ruess
On 6/19/2024 4:58 AM, Gerd Bayer wrote:
> Hi all,
>
> this all started with a single patch by Ben to enable writing a user-mode
> driver for a PCI device that requires 64bit register read/writes on s390.
> A quick grep showed that there are several other drivers for PCI devices
> in the kernel that use readq/writeq and eventually could use this, too.
> So we decided to propose this for general inclusion.
>
> A couple of suggestions for refactorizations by Jason Gunthorpe and Alex
> Williamson later [1], I arrived at this little series that avoids some
> code duplication in vfio_pci_core_do_io_rw().
> Also, I've added a small patch to correct the spelling in one of the
> declaration macros that was suggested by Ramesh Thomas [2]. However,
> after some discussions about making 8-byte accesses available for x86,
> Ramesh and I decided to do this in a separate patch [3].
The patchset looks good. I will post the x86 8-byte access enabling
patch as soon as I get enough testing done. Thanks.
Reviewed-by: Ramesh Thomas <ramesh.thomas@intel.com>
>
> This version was tested with a pass-through PCI device in a KVM guest
> and with explicit test reads of size 8, 16, 32, and 64 bit on s390.
> For 32bit architectures this has only been compile tested for the
> 32bit ARM architecture.
>
> Thank you,
> Gerd Bayer
>
>
> [1] https://lore.kernel.org/all/20240422153508.2355844-1-gbayer@linux.ibm.com/
> [2] https://lore.kernel.org/kvm/20240425165604.899447-1-gbayer@linux.ibm.com/T/#m1b51fe155c60d04313695fbee11a2ccea856a98c
> [3] https://lore.kernel.org/all/20240522232125.548643-1-ramesh.thomas@intel.com/
>
> Changes v5 -> v6:
> - restrict patch 3/3 to just the typo fix - no move of semicolons
>
> Changes v4 -> v5:
> - Make 8-byte accessors depend on the definitions of ioread64 and
> iowrite64, again. Ramesh agreed to sort these out for x86 separately.
>
> Changes v3 -> v4:
> - Make 64-bit accessors depend on CONFIG_64BIT (for x86, too).
> - Drop conversion of if-else if chain to switch-case.
> - Add patch to fix spelling of declaration macro.
>
> Changes v2 -> v3:
> - Introduce macro to generate body of different-size accesses in
> vfio_pci_core_do_io_rw (courtesy Alex Williamson).
> - Convert if-else if chain to a switch-case construct to better
> accommodate conditional compiles.
>
> Changes v1 -> v2:
> - On non 64bit architecture use at most 32bit accesses in
> vfio_pci_core_do_io_rw and describe that in the commit message.
> - Drop the run-time error on 32bit architectures.
> - The #endif splitting the "else if" is not really fortunate, but I'm
> open to suggestions.
>
>
> Ben Segal (1):
> vfio/pci: Support 8-byte PCI loads and stores
>
> Gerd Bayer (2):
> vfio/pci: Extract duplicated code into macro
> vfio/pci: Fix typo in macro to declare accessors
>
> drivers/vfio/pci/vfio_pci_rdwr.c | 122 ++++++++++++++++---------------
> include/linux/vfio_pci_core.h | 21 +++---
> 2 files changed, 74 insertions(+), 69 deletions(-)
>
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v6 0/3] vfio/pci: Support 8-byte PCI loads and stores
2024-06-21 21:50 ` Ramesh Thomas
@ 2024-12-03 18:01 ` Ramesh Thomas
0 siblings, 0 replies; 7+ messages in thread
From: Ramesh Thomas @ 2024-12-03 18:01 UTC (permalink / raw)
To: Gerd Bayer, Alex Williamson, Jason Gunthorpe, Niklas Schnelle
Cc: kvm, linux-s390, Ankit Agrawal, Yishai Hadas, Halil Pasic,
Ben Segal, Tian, Kevin, Julian Ruess
Hi Gerd, Jason and Alex,
I got delayed in sending the below mentioned patches as I was assigned
to other projects. I will shortly send the patch series that extends the
8-byte VFIO PCI read/write support to the x86 architecture.
Thanks,
Ramesh
On 6/21/2024 2:50 PM, Ramesh Thomas wrote:
> On 6/19/2024 4:58 AM, Gerd Bayer wrote:
>> Hi all,
>>
>> this all started with a single patch by Ben to enable writing a user-mode
>> driver for a PCI device that requires 64bit register read/writes on s390.
>> A quick grep showed that there are several other drivers for PCI devices
>> in the kernel that use readq/writeq and eventually could use this, too.
>> So we decided to propose this for general inclusion.
>>
>> A couple of suggestions for refactorizations by Jason Gunthorpe and Alex
>> Williamson later [1], I arrived at this little series that avoids some
>> code duplication in vfio_pci_core_do_io_rw().
>> Also, I've added a small patch to correct the spelling in one of the
>> declaration macros that was suggested by Ramesh Thomas [2]. However,
>> after some discussions about making 8-byte accesses available for x86,
>> Ramesh and I decided to do this in a separate patch [3].
>
> The patchset looks good. I will post the x86 8-byte access enabling
> patch as soon as I get enough testing done. Thanks.
>
> Reviewed-by: Ramesh Thomas <ramesh.thomas@intel.com>
>
>>
>> This version was tested with a pass-through PCI device in a KVM guest
>> and with explicit test reads of size 8, 16, 32, and 64 bit on s390.
>> For 32bit architectures this has only been compile tested for the
>> 32bit ARM architecture.
>>
>> Thank you,
>> Gerd Bayer
>>
>>
>> [1] https://lore.kernel.org/all/20240422153508.2355844-1-
>> gbayer@linux.ibm.com/
>> [2] https://lore.kernel.org/kvm/20240425165604.899447-1-
>> gbayer@linux.ibm.com/T/#m1b51fe155c60d04313695fbee11a2ccea856a98c
>> [3] https://lore.kernel.org/all/20240522232125.548643-1-
>> ramesh.thomas@intel.com/
>>
>> Changes v5 -> v6:
>> - restrict patch 3/3 to just the typo fix - no move of semicolons
>>
>> Changes v4 -> v5:
>> - Make 8-byte accessors depend on the definitions of ioread64 and
>> iowrite64, again. Ramesh agreed to sort these out for x86 separately.
>>
>> Changes v3 -> v4:
>> - Make 64-bit accessors depend on CONFIG_64BIT (for x86, too).
>> - Drop conversion of if-else if chain to switch-case.
>> - Add patch to fix spelling of declaration macro.
>>
>> Changes v2 -> v3:
>> - Introduce macro to generate body of different-size accesses in
>> vfio_pci_core_do_io_rw (courtesy Alex Williamson).
>> - Convert if-else if chain to a switch-case construct to better
>> accommodate conditional compiles.
>>
>> Changes v1 -> v2:
>> - On non 64bit architecture use at most 32bit accesses in
>> vfio_pci_core_do_io_rw and describe that in the commit message.
>> - Drop the run-time error on 32bit architectures.
>> - The #endif splitting the "else if" is not really fortunate, but I'm
>> open to suggestions.
>>
>>
>> Ben Segal (1):
>> vfio/pci: Support 8-byte PCI loads and stores
>>
>> Gerd Bayer (2):
>> vfio/pci: Extract duplicated code into macro
>> vfio/pci: Fix typo in macro to declare accessors
>>
>> drivers/vfio/pci/vfio_pci_rdwr.c | 122 ++++++++++++++++---------------
>> include/linux/vfio_pci_core.h | 21 +++---
>> 2 files changed, 74 insertions(+), 69 deletions(-)
>>
^ permalink raw reply [flat|nested] 7+ messages in thread