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From: "Edgecombe, Rick P" <rick.p.edgecombe@intel.com>
To: "binbin.wu@linux.intel.com" <binbin.wu@linux.intel.com>,
	"Gao, Chao" <chao.gao@intel.com>
Cc: "seanjc@google.com" <seanjc@google.com>,
	"Huang, Kai" <kai.huang@intel.com>,
	"Li, Xiaoyao" <xiaoyao.li@intel.com>,
	"Lindgren, Tony" <tony.lindgren@intel.com>,
	"Hunter, Adrian" <adrian.hunter@intel.com>,
	"Chatre, Reinette" <reinette.chatre@intel.com>,
	"pbonzini@redhat.com" <pbonzini@redhat.com>,
	"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
	"Yamahata, Isaku" <isaku.yamahata@intel.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"Zhao, Yan Y" <yan.y.zhao@intel.com>
Subject: Re: [PATCH v2 8/8] KVM: TDX: Handle TDX PV MMIO hypercall
Date: Fri, 14 Feb 2025 01:01:09 +0000	[thread overview]
Message-ID: <d79ebae6825071201f38bbae4af4df05d84c7ab5.camel@intel.com> (raw)
In-Reply-To: <aa6a2af0-fa4b-42a7-98d6-d295efbb2732@linux.intel.com>

On Fri, 2025-02-14 at 08:47 +0800, Binbin Wu wrote:
> 
> On 2/14/2025 5:41 AM, Edgecombe, Rick P wrote:
> > On Wed, 2025-02-12 at 10:39 +0800, Binbin Wu wrote:
> > > > IIRC, a TD-exit may occur due to an EPT MISCONFIG. Do you need to
> > > > distinguish
> > > > between a genuine EPT MISCONFIG and a morphed one, and handle them
> > > > differently?
> > > It will be handled separately, which will be in the last section of the KVM
> > > basic support.  But the v2 of "the rest" section is on hold because there is
> > > a discussion related to MTRR MSR handling:
> > > https://lore.kernel.org/all/20250201005048.657470-1-seanjc@google.com/
> > > Want to send the v2 of "the rest" section after the MTRR discussion is
> > > finalized.
> > I think we can just put back the original MTRR code (post KVM MTRR removal
> > version) for the next posting of the rest. The reason being Sean was pointing
> > that it is more architecturally correct given that the CPUID bit is exposed. So
> > we will need that regardless of the guest solution.
> The original MTRR code before removing is:
> https://lore.kernel.org/kvm/81119d66392bc9446340a16f8a532c7e1b2665a2.1708933498.git.isaku.yamahata@intel.com/
> 
> It enforces WB as default memtype and disables fixed/variable range MTRRs.
> That means this solution doesn't allow guest to use MTRRs as a communication
> channel if the guest firmware wants to program some ranges to UC for legacy
> devices.

I'm talking about the internal version that existed after KVM removed MTRRs for
normal VMs. We are not talking about adding back KVM MTRRs.

> 
> 
> How about to allow TDX guests to access MTRR MSRs as what KVM does for
> normal VMs?
> 
> Guest kernels may use MTRRs as a crutch to get the desired memtype for devices.
> E.g., in most KVM-based setups, legacy devices such as the HPET and TPM are
> enumerated via ACPI.  And in Linux kernel, for unknown reasons, ACPI auto-maps
> such devices as WB, whereas the dedicated device drivers map memory as WC or
> UC.  The ACPI mappings rely on firmware to configure PCI hole (and other device
> memory) to be UC in the MTRRs to end up UC-, which is compatible with the
> drivers' requested WC/UC-.
> 
> So KVM needs to allow guests to program the desired value in MTRRs in case
> guests want to use MTRRs as a communication channel between guest firmware
> and the kernel.
> 
> Allow TDX guests to access MTRR MSRs as what KVM does for normal VMs, i.e.,
> KVM emulates accesses to MTRR MSRs, but doesn't virtualize guest MTRR memory
> types.  One open is whether enforce the value of default MTRR memtype as WB.

This is basically what we had previously (internally), right?

> 
> However, TDX disallows toggling CR0.CD.  If a TDX guest wants to use MTRRs
> as the communication channel, it should skip toggling CR0.CD when it
> programs MTRRs both in guest firmware and guest kernel.  For a guest, there
> is no reason to disable caches because it's in a virtual environment.  It
> makes sense for guest firmware/kernel to skip toggling CR0.CD when it
> detects it's running as a TDX guest.

I don't see why we have to tie exposing MTRR to a particular solution for the
guest and bios. Let's focus on the work we know we need regardless for KVM.

  reply	other threads:[~2025-02-14  1:01 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-11  2:54 [PATCH v2 0/8] KVM: TDX: TDX hypercalls may exit to userspace Binbin Wu
2025-02-11  2:54 ` [PATCH v2 1/8] KVM: x86: Have ____kvm_emulate_hypercall() read the GPRs Binbin Wu
2025-02-11  5:05   ` Huang, Kai
2025-02-11 10:23   ` Xiaoyao Li
2025-02-12  1:32     ` Binbin Wu
2025-02-12  3:12       ` Xiaoyao Li
2025-02-11  2:54 ` [PATCH v2 2/8] KVM: TDX: Add a place holder to handle TDX VM exit Binbin Wu
2025-02-11  2:54 ` [PATCH v2 3/8] KVM: TDX: Add a place holder for handler of TDX hypercalls (TDG.VP.VMCALL) Binbin Wu
2025-02-11  8:41   ` Chao Gao
2025-02-11  9:08     ` Binbin Wu
2025-02-11 23:46     ` Sean Christopherson
2025-02-12  2:21       ` Binbin Wu
2025-02-11  2:54 ` [PATCH v2 4/8] KVM: TDX: Handle KVM hypercall with TDG.VP.VMCALL Binbin Wu
2025-02-11 23:48   ` Sean Christopherson
2025-02-11  2:54 ` [PATCH v2 5/8] KVM: TDX: Handle TDG.VP.VMCALL<MapGPA> Binbin Wu
2025-02-11  6:54   ` Yan Zhao
2025-02-11  8:11     ` Binbin Wu
2025-02-11  8:59       ` Chao Gao
2025-02-12  0:46         ` Sean Christopherson
2025-02-12  5:16           ` Binbin Wu
2025-02-12 18:56             ` Sean Christopherson
2025-02-13  3:23               ` Binbin Wu
2025-02-13  5:11                 ` Binbin Wu
2025-02-13 15:17                   ` Sean Christopherson
2025-02-17  3:41                     ` Binbin Wu
2025-02-19  0:29                       ` Sean Christopherson
2025-02-19  0:49                         ` Binbin Wu
2025-02-11  2:54 ` [PATCH v2 6/8] KVM: TDX: Handle TDG.VP.VMCALL<ReportFatalError> Binbin Wu
2025-02-12  0:18   ` Sean Christopherson
2025-02-12  5:37     ` Binbin Wu
2025-02-12 13:53       ` Sean Christopherson
2025-02-11  2:54 ` [PATCH v2 7/8] KVM: TDX: Handle TDX PV port I/O hypercall Binbin Wu
2025-02-11  2:54 ` [PATCH v2 8/8] KVM: TDX: Handle TDX PV MMIO hypercall Binbin Wu
2025-02-12  2:28   ` Chao Gao
2025-02-12  2:39     ` Binbin Wu
2025-02-13 21:41       ` Edgecombe, Rick P
2025-02-14  0:47         ` Binbin Wu
2025-02-14  1:01           ` Edgecombe, Rick P [this message]
2025-02-14  1:20             ` Binbin Wu

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