Re: [PATCH v5 1/8] KVM: x86: Carve out PML flush routine

["Nikunj A. Dadhania" <nikunj@amd.com>]

On 1/12/2026 3:32 PM, Huang, Kai wrote:
> On Mon, 2026-01-05 at 06:36 +0000, Nikunj A Dadhania wrote:
>> Move the PML (Page Modification Logging) buffer flushing logic from
>> VMX-specific code to common x86 KVM code to enable reuse by SVM and avoid
>> code duplication.
>>
>> The AMD SVM PML implementations share the same behavior as VMX PML:
>>  1) The PML buffer is a 4K page with 512 entries
>>  2) Hardware records dirty GPAs in reverse order (from index 511 to 0)
>>  3) Hardware clears bits 11:0 when recording GPAs
>>
>> The PML constants (PML_LOG_NR_ENTRIES and PML_HEAD_INDEX) are moved from
>> vmx.h to x86.h to make them available to both VMX and SVM.
> 
> Nit:
> 
> If a new version is needed, you can use imperative mode for the above
> paragraph:
> 
>   Move PML constants (...) from vmx.h to x86.h to ...
> 
> Or IMHO you can just remove this paragraph, because the new
> kvm_flush_pml_buffer() in x86.c uses both PML constants so the move is
> implied actually.

Sure, will remove the paragraph as it is implied.

> 
>>
>> No functional change intended for VMX, except tone down the WARN_ON() to
>> WARN_ON_ONCE() for the page alignment check. If hardware exhibits this
>> behavior once, it's likely to occur repeatedly, so use WARN_ON_ONCE() to
>> avoid log flooding while still capturing the unexpected condition.
>>
>> The refactoring prepares for SVM to leverage the same PML flushing
>> implementation.
>>
>> Signed-off-by: Nikunj A Dadhania <nikunj@amd.com>
> 
> Reviewed-by: Kai Huang <kai.huang@intel.com>

Thanks
Nikunj