From: Like Xu <like.xu.linux@gmail.com>
To: Jim Mattson <jmattson@google.com>, David Dunn <daviddunn@google.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Joerg Roedel <joro@8bytes.org>,
Kim Phillips <kim.phillips@amd.com>,
Maxim Levitsky <mlevitsk@redhat.com>,
Sean Christopherson <seanjc@google.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] KVM: x86/pmu: Fix reserved bits for AMD PerfEvtSeln register
Date: Wed, 16 Feb 2022 15:47:33 +0800 [thread overview]
Message-ID: <dc14c98c-e35a-95c0-83dd-13b5f7cffc03@gmail.com> (raw)
In-Reply-To: <CALMp9eTONaviuz-NnPUP2=MEOb8ZBkZ7u_ZQBWBUne-i6cRUkA@mail.gmail.com>
On 12/2/2022 4:39 pm, Jim Mattson wrote:
>> - pmu->reserved_bits = 0xffffffff00200000ull;
>> + pmu->reserved_bits = 0xfffffff000280000ull;
> Bits 40 and 41 are guest mode and host mode. They cannot be reserved
> if the guest supports nested SVM.
>
Indeed, we need (some hands) to do more pmu tests on nested SVM.
next prev parent reply other threads:[~2022-02-16 7:47 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-18 13:03 [PATCH] KVM: x86/pmu: Fix reserved bits for AMD PerfEvtSeln register Like Xu
2021-11-18 13:23 ` Paolo Bonzini
2021-11-18 14:43 ` Paolo Bonzini
2022-02-12 8:39 ` Jim Mattson
2022-02-16 7:47 ` Like Xu [this message]
2022-02-25 22:26 ` Jim Mattson
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