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X-CSE-ConnectionGUID: xw/ulTHETMGydPkFRnH7FQ== X-CSE-MsgGUID: rUamgcC4SvK2JeVd4Zw7iQ== X-IronPort-AV: E=McAfee;i="6800,10657,11459"; a="51487124" X-IronPort-AV: E=Sophos;i="6.16,224,1744095600"; d="scan'208";a="51487124" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jun 2025 23:18:46 -0700 X-CSE-ConnectionGUID: ANAFZMdBRW+xc9QcNP75aw== X-CSE-MsgGUID: 7eTE/kRZScapcKfNoDAhxw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,224,1744095600"; d="scan'208";a="151743551" Received: from dapengmi-mobl1.ccr.corp.intel.com (HELO [10.124.245.144]) ([10.124.245.144]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jun 2025 23:18:43 -0700 Message-ID: Date: Tue, 10 Jun 2025 14:18:40 +0800 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [kvm-unit-tests PATCH 05/16] x86: Implement get_supported_xcr0() using X86_PROPERTY_SUPPORTED_XCR0_{LO,HI} To: Sean Christopherson , Andrew Jones , Janosch Frank , Claudio Imbrenda , =?UTF-8?Q?Nico_B=C3=B6hr?= , Paolo Bonzini Cc: kvm-riscv@lists.infradead.org, linux-s390@vger.kernel.org, kvm@vger.kernel.org References: <20250529221929.3807680-1-seanjc@google.com> <20250529221929.3807680-6-seanjc@google.com> Content-Language: en-US From: "Mi, Dapeng" In-Reply-To: <20250529221929.3807680-6-seanjc@google.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 5/30/2025 6:19 AM, Sean Christopherson wrote: > Use X86_PROPERTY_SUPPORTED_XCR0_{LO,HI} to implement get_supported_xcr0(). > > Opportunistically rename the helper and move it to processor.h. > > Signed-off-by: Sean Christopherson > --- > lib/x86/processor.h | 9 +++++++++ > x86/xsave.c | 11 +---------- > 2 files changed, 10 insertions(+), 10 deletions(-) > > diff --git a/lib/x86/processor.h b/lib/x86/processor.h > index 8c6f28a3..cbfd2ee1 100644 > --- a/lib/x86/processor.h > +++ b/lib/x86/processor.h > @@ -442,6 +442,15 @@ static inline u8 cpuid_maxphyaddr(void) > return this_cpu_property(X86_PROPERTY_MAX_PHY_ADDR); > } > > +static inline u64 this_cpu_supported_xcr0(void) > +{ > + if (!this_cpu_has_p(X86_PROPERTY_SUPPORTED_XCR0_LO)) > + return 0; > + > + return (u64)this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_LO) | > + ((u64)this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32); > +} > + > struct far_pointer32 { > u32 offset; > u16 selector; > diff --git a/x86/xsave.c b/x86/xsave.c > index 5d80f245..cc8e3a0a 100644 > --- a/x86/xsave.c > +++ b/x86/xsave.c > @@ -8,15 +8,6 @@ > #define uint64_t unsigned long long > #endif > > -static uint64_t get_supported_xcr0(void) > -{ > - struct cpuid r; > - r = cpuid_indexed(0xd, 0); > - printf("eax %x, ebx %x, ecx %x, edx %x\n", > - r.a, r.b, r.c, r.d); > - return r.a + ((u64)r.d << 32); > -} > - > #define XCR_XFEATURE_ENABLED_MASK 0x00000000 > #define XCR_XFEATURE_ILLEGAL_MASK 0x00000010 > > @@ -33,7 +24,7 @@ static void test_xsave(void) > > printf("Legal instruction testing:\n"); > > - supported_xcr0 = get_supported_xcr0(); > + supported_xcr0 = this_cpu_supported_xcr0(); > printf("Supported XCR0 bits: %#lx\n", supported_xcr0); > > test_bits = XSTATE_FP | XSTATE_SSE; Reviewed-by: Dapeng Mi