From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Sascha Bischoff <Sascha.Bischoff@arm.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"kvmarm@lists.linux.dev" <kvmarm@lists.linux.dev>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>
Cc: nd <nd@arm.com>, "maz@kernel.org" <maz@kernel.org>,
"oliver.upton@linux.dev" <oliver.upton@linux.dev>,
Joey Gouly <Joey.Gouly@arm.com>,
"yuzenghui@huawei.com" <yuzenghui@huawei.com>,
"will@kernel.org" <will@kernel.org>,
"tglx@linutronix.de" <tglx@linutronix.de>,
"lpieralisi@kernel.org" <lpieralisi@kernel.org>,
Timothy Hayes <Timothy.Hayes@arm.com>
Subject: Re: [PATCH 3/5] arm64: cpucaps: Add GICv5 Legacy vCPU interface (GCIE_LEGACY) capability
Date: Tue, 2 Sep 2025 09:23:34 +0100 [thread overview]
Message-ID: <e823610a-e145-4627-9968-6d2dcc873184@arm.com> (raw)
In-Reply-To: <20250828105925.3865158-4-sascha.bischoff@arm.com>
On 28/08/2025 11:59, Sascha Bischoff wrote:
> Implement the GCIE_LEGACY capability as a system feature to be able to
> check for support from KVM. The type is explicitly
> ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, which means that the capability
> is enabled early if all boot CPUs support it. Additionally, if this
> capability is enabled during boot, it prevents late onlining of CPUs
> that lack it, thereby avoiding potential mismatched configurations
> which would break KVM.
>
> Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
> ---
> arch/arm64/kernel/cpufeature.c | 15 +++++++++++++++
> arch/arm64/tools/cpucaps | 1 +
> 2 files changed, 16 insertions(+)
>
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 9ad065f15f1d..afb3b10afd75 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -2520,6 +2520,15 @@ test_has_mpam_hcr(const struct arm64_cpu_capabilities *entry, int scope)
> return idr & MPAMIDR_EL1_HAS_HCR;
> }
>
> +static bool
> +test_has_gicv5_legacy(const struct arm64_cpu_capabilities *entry, int scope)
> +{
> + if (!this_cpu_has_cap(ARM64_HAS_GICV5_CPUIF))
> + return false;
> +
> + return !!(read_sysreg_s(SYS_ICC_IDR0_EL1) & ICC_IDR0_EL1_GCIE_LEGACY);
> +}
> +
> static const struct arm64_cpu_capabilities arm64_features[] = {
> {
> .capability = ARM64_ALWAYS_BOOT,
> @@ -3131,6 +3140,12 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
> .matches = has_cpuid_feature,
> ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, GCIE, IMP)
> },
> + {
> + .desc = "GICv5 Legacy vCPU interface",
> + .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE,
This is the right type for the capability intended, running the test on
each boot time CPUs and setting the cap accordingly.
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
next prev parent reply other threads:[~2025-09-02 8:23 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-28 10:59 [PATCH 0/5] KVM: arm64: GICv5 legacy (GCIE_LEGACY) NV enablement and cleanup Sascha Bischoff
2025-08-28 10:59 ` [PATCH 1/5] KVM: arm64: Allow ICC_SRE_EL2 accesses on a GICv5 host Sascha Bischoff
2025-08-28 14:05 ` Marc Zyngier
2025-08-28 10:59 ` [PATCH 2/5] KVM: arm64: Enable nested for GICv5 host with FEAT_GCIE_LEGACY Sascha Bischoff
2025-08-28 10:59 ` [PATCH 4/5] KVM: arm64: Use ARM64_HAS_GICV5_LEGACY for GICv5 probing Sascha Bischoff
2025-08-28 10:59 ` [PATCH 3/5] arm64: cpucaps: Add GICv5 Legacy vCPU interface (GCIE_LEGACY) capability Sascha Bischoff
2025-09-02 8:23 ` Suzuki K Poulose [this message]
2025-08-28 10:59 ` [PATCH 5/5] irqchip/gic-v5: Drop has_gcie_v3_compat from gic_kvm_info Sascha Bischoff
2025-09-03 12:07 ` Thomas Gleixner
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