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X-CSE-ConnectionGUID: 3UznumaHTH6dAR9CdpWONg== X-CSE-MsgGUID: ZY8YMweDTwGWmrRt0EoPzw== X-IronPort-AV: E=McAfee;i="6800,10657,11460"; a="51747313" X-IronPort-AV: E=Sophos;i="6.16,227,1744095600"; d="scan'208";a="51747313" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2025 00:15:05 -0700 X-CSE-ConnectionGUID: JU3XRYaKR56sOKqNXnoqBQ== X-CSE-MsgGUID: b9Lg0LNyTAGkxPw6lX9asw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,227,1744095600"; d="scan'208";a="177997213" Received: from unknown (HELO [10.238.0.239]) ([10.238.0.239]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2025 00:15:02 -0700 Message-ID: Date: Wed, 11 Jun 2025 15:14:59 +0800 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 01/32] KVM: SVM: Disable interception of SPEC_CTRL iff the MSR exists for the guest From: Binbin Wu To: Sean Christopherson Cc: Paolo Bonzini , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Chao Gao , Borislav Petkov , Xin Li , Dapeng Mi , Francesco Lavra , Manali Shukla References: <20250610225737.156318-1-seanjc@google.com> <20250610225737.156318-2-seanjc@google.com> <629e0dc3-49b4-45f5-aeaa-8a9109e81d14@linux.intel.com> Content-Language: en-US In-Reply-To: <629e0dc3-49b4-45f5-aeaa-8a9109e81d14@linux.intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 6/11/2025 12:38 PM, Binbin Wu wrote: > > > On 6/11/2025 6:57 AM, Sean Christopherson wrote: >> Disable interception of SPEC_CTRL when the CPU virtualizes (i.e. context >> switches) SPEC_CTRL if and only if the MSR exists according to the vCPU's >> CPUID model.  Letting the guest access SPEC_CTRL is generally benign, but >> the guest would see inconsistent behavior if KVM happened to emulate an >> access to the MSR. >> >> Fixes: d00b99c514b3 ("KVM: SVM: Add support for Virtual SPEC_CTRL") >> Reported-by: Chao Gao >> Signed-off-by: Sean Christopherson >> --- >>   arch/x86/kvm/svm/svm.c | 9 ++++++--- >>   1 file changed, 6 insertions(+), 3 deletions(-) >> >> diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c >> index 0ad1a6d4fb6d..21e745acebc3 100644 >> --- a/arch/x86/kvm/svm/svm.c >> +++ b/arch/x86/kvm/svm/svm.c >> @@ -1362,11 +1362,14 @@ static void init_vmcb(struct kvm_vcpu *vcpu) >>       svm_recalc_instruction_intercepts(vcpu, svm); >>         /* >> -     * If the host supports V_SPEC_CTRL then disable the interception >> -     * of MSR_IA32_SPEC_CTRL. >> +     * If the CPU virtualizes MSR_IA32_SPEC_CTRL, i.e. KVM doesn't need to >> +     * manually context switch the MSR, immediately configure interception >> +     * of SPEC_CTRL, without waiting for the guest to access the MSR. >>        */ >>       if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL)) >> -        set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1); >> +        set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, >> +                     guest_has_spec_ctrl_msr(vcpu), >> +                     guest_has_spec_ctrl_msr(vcpu)); > Side topic, not related to this patch directly. > > Setting to 1 for set_msr_interception() means to disable interception. > The name of the function seems a bit counterintuitive to me. > Maybe some description for the function can help people not familiar with > SVM code without further checking the implementation? Oh, please ignore it. A later patch in this patch set has handled it. > > >>         if (kvm_vcpu_apicv_active(vcpu)) >>           avic_init_vmcb(svm, vmcb); > >