From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: [PATCH v1 1/3] kvm: svm: Add support for additional SVM NPF error codes Date: Tue, 22 Nov 2016 23:29:56 +0100 Message-ID: References: <147916172660.16347.15695649975899246333.stgit@brijesh-build-machine> <147916173923.16347.14406683681257344312.stgit@brijesh-build-machine> <0be2f3e1-8ee4-9b40-3837-13def54e9f07@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Cc: rkrcmar@redhat.com, joro@8bytes.org, x86@kernel.org, linux-kernel@vger.kernel.org, mingo@redhat.com, hpa@zytor.com, tglx@linutronix.de, bp@suse.de To: Tom Lendacky , Brijesh Singh , kvm@vger.kernel.org Return-path: In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org List-Id: kvm.vger.kernel.org On 22/11/2016 23:15, Tom Lendacky wrote: > > 2) what bit is set if the processor is reading the PDPTEs of a 32-bit > > PAE guest? > > I believe that bit 33 will be set. The PDPE's are considered guest > tables and are read during a guest table walk (see APM vol2 section > 15.25.10). Note that this is slightly different than the bare-metal > behavior of legacy PAE mode as APM describes. I'll try to test this > and verify it. No big deal, indeed it's a bit different from Intel which caches the four PDPEs, but it's enough to know that bit 33 will be set. Paolo