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([2001:b07:6468:f312:5e2c:eb9a:a8b6:fd3e]) by smtp.googlemail.com with ESMTPSA id r18-20020adfe692000000b00238df11940fsm1788044wrm.16.2022.11.11.03.57.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 11 Nov 2022 03:57:59 -0800 (PST) Message-ID: Date: Fri, 11 Nov 2022 12:57:58 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.0 Subject: Re: [PATCH 5/6] KVM: x86/VMX: add kvm_vmx_reinject_nmi_irq() for NMI/IRQ reinjection Content-Language: en-US To: Peter Zijlstra , "H. Peter Anvin" Cc: Sean Christopherson , "Li, Xin3" , "linux-kernel@vger.kernnel.org" , "x86@kernel.org" , "kvm@vger.kernel.org" , "tglx@linutronix.de" , "mingo@redhat.com" , "bp@alien8.de" , "dave.hansen@linux.intel.com" , "Tian, Kevin" References: <20221110055347.7463-1-xin3.li@intel.com> <20221110055347.7463-6-xin3.li@intel.com> <3A1B7743-9448-405A-8BE4-E1BDAB4D62F8@zytor.com> From: Paolo Bonzini In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On 11/11/22 11:45, Peter Zijlstra wrote: >> What is "correct" in this context? > > I don't know since I don't really speak virt, but I could image the > regset that would match the vmrun (or whatever intel decided to call > that again) instruction. Right now it is not exactly that but close. The RIP is somewhere in vmx_do_interrupt_nmi_irqoff; CS/SS are correct (i.e. it's not like they point to guest values!) and other registers including RSP and RFLAGS are consistent with the RIP. >> Currently KVM basically stuff random data into pt_regs; this at least >> makes it explicitly zero. > > 🙁 Both is broken. Once again proving to me that virt is a bunch of > duck-tape at best. Except currently it is not random. At least I'm not alone in sometimes thinking I understand stuff when I actually don't. Zero is just wrong, I agree. Xin, if you don't want to poke at the IDT you need to build the pt_regs and pass them to the function you add in patch 5. In order to make it like Peter wants it, then: 1) for the flags just use X86_EFLAGS_FIXED 2) for CS/SS segment selectors use __KERNEL_CS and __KERNEL_DS 3) the RIP/RSP can be found respectively in (unsigned long)vmx_vmexit vmx->loaded_vmcs->host_state.rsp 4) the other registers can be taken from vcpu->arch.regs But I am not sure it's an improvement. It may be okay to zero the registers, but setting CS/RIP/SS/RSP/RFLAGS to the actual processor values in vmx_do_interrupt_nmi_irqoff is safer. I'm not sure who would set orig_rax, but I haven't looked too closely. Perhaps that's not a problem, but if so it has to be documented in the commit message. Paolo