* [PATCH v8 00/48] single-binary: compile target/arm twice
@ 2025-05-12 18:04 Pierrick Bouvier
2025-05-12 18:04 ` [PATCH v8 01/48] target/arm: Replace target_ulong -> vaddr for HWBreakpoint Pierrick Bouvier
` (47 more replies)
0 siblings, 48 replies; 71+ messages in thread
From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm,
Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier
More work toward single-binary.
Some files have external dependencies for the single-binary:
- target/arm/gdbstub.c: gdbhelpers
- target/arm/arm-qmp-cmds.c: qapi
- target/arm/tcg/translate*: need deep cleanup in include/tcg
- target/arm/tcg/cpu*: need TargetInfo implemented for arm/aarch64
- target/arm/tcg/*-helper*: need deeper split between aarch64 and arm code
They will not be ported in this series.
Built on {linux, windows, macos} x {x86_64, aarch64}
Fully tested on linux x {x86_64, aarch64}
Series is now tested and fully reviewed. Thanks for pulling it.
v8
--
- rebase on top of master
v7
--
- rebase on top of master
- removed patch to apply target config for picking files in libsystem/libuser,
since it was the only one not reviewed.
v6
--
CI: https://github.com/pbo-linaro/qemu/actions/runs/14844742069/job/41675865456
- Replace target_ulong -> vaddr for HWBreakpoint (Philippe)
- build target/arm/tcg/crypto_helper.c once (Richard)
- build target/arm/tcg/tlb-insns for system only (Richard)
- build target/arm/tcg/arith_helper once (Richard)
v5
--
CI: https://github.com/pbo-linaro/qemu/actions/runs/14825451208/job/41617949501
- Do not define a separate vaddr type in tcg, simply alias to i32/i64 (Richard)
- target/arm/tcg/crypto_helper.c
- target/arm/tcg/hflags.c
- target/arm/tcg/iwmmxt_helper.c
- target/arm/tcg/neon_helper.c
- target/arm/tcg/tlb_helper.c
- target/arm/tcg/tlb-insns.c
- target/arm/tcg/arith_helper.c
- target/arm/tcg/vfp_helper.c
v4
--
CI: https://github.com/pbo-linaro/qemu/actions/runs/14816460393/job/41597560792
- add patch to apply target config for picking files in libsystem/libuser
Useful for Philippe series for semihosting:
https://lore.kernel.org/qemu-devel/20250502220524.81548-1-philmd@linaro.org/T/#me750bbaeeba4d16791121fe98b44202afaec4068
- update some patches description (Philippe & Richard)
- tcg: introduce vaddr type (Richard)
- modify concerned helpers to use vaddr instead of i64 (Richard)
- use int64_t instead of uint64_t for top_bits in ptw.c (Philippe)
- arm_casq_ptw: use CONFIG_ATOMIC64 instead of TARGET_AARCH64 and comment why
(Richard)
- target/arm/machine.c
v3
--
CI: https://github.com/pbo-linaro/qemu/actions/runs/14765763846/job/41456754153
- Add missing license for new files (Richard)
- target/arm/debug_helper.c
- target/arm/helper.c
- target/arm/vfp_fpscr.c
- target/arm/arch_dump.c
- target/arm/arm-powerctl.c
- target/arm/cortex-regs.c
- target/arm/ptw.c
- target/arm/kvm-stub.c
v2
--
- Remove duplication of kvm struct and constant (Alex)
- Use target_big_endian() (Anton)
v1
--
- target/arm/cpu.c
Philippe Mathieu-Daudé (1):
target/arm: Replace target_ulong -> vaddr for HWBreakpoint
Pierrick Bouvier (47):
include/system/hvf: missing vaddr include
meson: add common libs for target and target_system
target/arm: move kvm stubs and remove CONFIG_KVM from kvm_arm.h
target/arm/kvm-stub: add kvm_arm_reset_vcpu stub
target/arm/cpu: move arm_cpu_kvm_set_irq to kvm.c
target/arm/cpu: remove TARGET_BIG_ENDIAN dependency
target/arm/cpu: remove TARGET_AARCH64 around aarch64_cpu_dump_state
common
target/arm/cpu: remove TARGET_AARCH64 in arm_cpu_finalize_features
target/arm/cpu: compile file twice (user, system) only
target/arm/cpu32-stubs.c: compile file twice (user, system)
tcg: add vaddr type for helpers
target/arm/helper: use vaddr instead of target_ulong for
exception_pc_alignment
target/arm/helper: use vaddr instead of target_ulong for probe_access
target/arm/helper: extract common helpers
target/arm/debug_helper: only include common helpers
target/arm/debug_helper: remove target_ulong
target/arm/debug_helper: compile file twice (user, system)
target/arm/helper: restrict include to common helpers
target/arm/helper: replace target_ulong by vaddr
target/arm/helper: expose aarch64 cpu registration
target/arm/helper: remove remaining TARGET_AARCH64
target/arm/helper: compile file twice (user, system)
target/arm/vfp_fpscr: compile file twice (user, system)
target/arm/arch_dump: remove TARGET_AARCH64 conditionals
target/arm/arch_dump: compile file once (system)
target/arm/arm-powerctl: compile file once (system)
target/arm/cortex-regs: compile file once (system)
target/arm/ptw: replace target_ulong with int64_t
target/arm/ptw: replace TARGET_AARCH64 by CONFIG_ATOMIC64 from
arm_casq_ptw
target/arm/ptw: compile file once (system)
target/arm/meson: accelerator files are not needed in user mode
target/arm/kvm-stub: compile file once (system)
target/arm/machine: reduce migration include to avoid target specific
definitions
target/arm/machine: remove TARGET_AARCH64 from migration state
target/arm/machine: move cpu_post_load kvm bits to
kvm_arm_cpu_post_load function
target/arm/kvm-stub: add missing stubs
target/arm/machine: compile file once (system)
target/arm/tcg/vec_internal: use forward declaration for CPUARMState
target/arm/tcg/crypto_helper: compile file once
target/arm/tcg/hflags: compile file twice (system, user)
target/arm/tcg/iwmmxt_helper: compile file twice (system, user)
target/arm/tcg/neon_helper: compile file twice (system, user)
target/arm/tcg/tlb_helper: compile file twice (system, user)
target/arm/helper: restrict define_tlb_insn_regs to system target
target/arm/tcg/tlb-insns: compile file once (system)
target/arm/tcg/arith_helper: compile file once
target/arm/tcg/vfp_helper: compile file twice (system, user)
meson.build | 78 ++-
include/system/hvf.h | 1 +
include/tcg/tcg-op-common.h | 1 +
include/tcg/tcg.h | 14 +
target/arm/helper.h | 1152 +------------------------------
target/arm/internals.h | 6 +-
target/arm/kvm_arm.h | 87 +--
target/arm/tcg/helper.h | 1153 ++++++++++++++++++++++++++++++++
target/arm/tcg/vec_internal.h | 2 +
include/exec/helper-head.h.inc | 11 +
target/arm/arch_dump.c | 6 -
target/arm/cpu.c | 47 +-
target/arm/cpu32-stubs.c | 26 +
target/arm/debug_helper.c | 6 +-
target/arm/helper.c | 24 +-
target/arm/hyp_gdbstub.c | 6 +-
target/arm/kvm-stub.c | 97 +++
target/arm/kvm.c | 42 +-
target/arm/machine.c | 15 +-
target/arm/ptw.c | 6 +-
target/arm/tcg/arith_helper.c | 5 +-
target/arm/tcg/crypto_helper.c | 6 +-
target/arm/tcg/hflags.c | 4 +-
target/arm/tcg/iwmmxt_helper.c | 4 +-
target/arm/tcg/neon_helper.c | 4 +-
target/arm/tcg/op_helper.c | 2 +-
target/arm/tcg/tlb-insns.c | 7 -
target/arm/tcg/tlb_helper.c | 5 +-
target/arm/tcg/translate-a64.c | 2 +-
target/arm/tcg/translate.c | 2 +-
target/arm/tcg/vfp_helper.c | 4 +-
tcg/tcg.c | 5 +
target/arm/meson.build | 41 +-
target/arm/tcg/meson.build | 29 +-
34 files changed, 1519 insertions(+), 1381 deletions(-)
create mode 100644 target/arm/tcg/helper.h
create mode 100644 target/arm/cpu32-stubs.c
--
2.47.2
^ permalink raw reply [flat|nested] 71+ messages in thread* [PATCH v8 01/48] target/arm: Replace target_ulong -> vaddr for HWBreakpoint 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 02/48] include/system/hvf: missing vaddr include Pierrick Bouvier ` (46 subsequent siblings) 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier From: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/internals.h | 6 +++--- target/arm/hyp_gdbstub.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 660d3a88e07..5b421bc4ecd 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1949,9 +1949,9 @@ extern GArray *hw_breakpoints, *hw_watchpoints; #define get_hw_bp(i) (&g_array_index(hw_breakpoints, HWBreakpoint, i)) #define get_hw_wp(i) (&g_array_index(hw_watchpoints, HWWatchpoint, i)) -bool find_hw_breakpoint(CPUState *cpu, target_ulong pc); -int insert_hw_breakpoint(target_ulong pc); -int delete_hw_breakpoint(target_ulong pc); +bool find_hw_breakpoint(CPUState *cpu, vaddr pc); +int insert_hw_breakpoint(vaddr pc); +int delete_hw_breakpoint(vaddr pc); bool check_watchpoint_in_range(int i, vaddr addr); CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, vaddr addr); diff --git a/target/arm/hyp_gdbstub.c b/target/arm/hyp_gdbstub.c index 0512d67f8cf..bb5969720ce 100644 --- a/target/arm/hyp_gdbstub.c +++ b/target/arm/hyp_gdbstub.c @@ -54,7 +54,7 @@ GArray *hw_breakpoints, *hw_watchpoints; * here so future PC comparisons will work properly. */ -int insert_hw_breakpoint(target_ulong addr) +int insert_hw_breakpoint(vaddr addr) { HWBreakpoint brk = { .bcr = 0x1, /* BCR E=1, enable */ @@ -80,7 +80,7 @@ int insert_hw_breakpoint(target_ulong addr) * Delete a breakpoint and shuffle any above down */ -int delete_hw_breakpoint(target_ulong pc) +int delete_hw_breakpoint(vaddr pc) { int i; for (i = 0; i < hw_breakpoints->len; i++) { @@ -226,7 +226,7 @@ int delete_hw_watchpoint(vaddr addr, vaddr len, int type) return -ENOENT; } -bool find_hw_breakpoint(CPUState *cpu, target_ulong pc) +bool find_hw_breakpoint(CPUState *cpu, vaddr pc) { int i; -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v8 02/48] include/system/hvf: missing vaddr include 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 01/48] target/arm: Replace target_ulong -> vaddr for HWBreakpoint Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-13 9:58 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 03/48] meson: add common libs for target and target_system Pierrick Bouvier ` (45 subsequent siblings) 47 siblings, 1 reply; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier On MacOS x86_64: In file included from ../target/i386/hvf/x86_task.c:13: /Users/runner/work/qemu/qemu/include/system/hvf.h:42:5: error: unknown type name 'vaddr' vaddr pc; ^ /Users/runner/work/qemu/qemu/include/system/hvf.h:43:5: error: unknown type name 'vaddr' vaddr saved_insn; ^ /Users/runner/work/qemu/qemu/include/system/hvf.h:45:5: error: type name requires a specifier or qualifier QTAILQ_ENTRY(hvf_sw_breakpoint) entry; ^ /Users/runner/work/qemu/qemu/include/system/hvf.h:45:18: error: a parameter list without types is only allowed in a function definition QTAILQ_ENTRY(hvf_sw_breakpoint) entry; ^ /Users/runner/work/qemu/qemu/include/system/hvf.h:45:36: error: expected ';' at end of declaration list QTAILQ_ENTRY(hvf_sw_breakpoint) entry; Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- include/system/hvf.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/system/hvf.h b/include/system/hvf.h index 7b45a2e1988..a9a502f0c8f 100644 --- a/include/system/hvf.h +++ b/include/system/hvf.h @@ -17,6 +17,7 @@ #include "qemu/queue.h" #include "exec/vaddr.h" #include "qom/object.h" +#include "exec/vaddr.h" #ifdef COMPILING_PER_TARGET # ifdef CONFIG_HVF -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v8 02/48] include/system/hvf: missing vaddr include 2025-05-12 18:04 ` [PATCH v8 02/48] include/system/hvf: missing vaddr include Pierrick Bouvier @ 2025-05-13 9:58 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 71+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-13 9:58 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson On 12/5/25 20:04, Pierrick Bouvier wrote: > On MacOS x86_64: > In file included from ../target/i386/hvf/x86_task.c:13: > /Users/runner/work/qemu/qemu/include/system/hvf.h:42:5: error: unknown type name 'vaddr' > vaddr pc; > ^ > /Users/runner/work/qemu/qemu/include/system/hvf.h:43:5: error: unknown type name 'vaddr' > vaddr saved_insn; > ^ > /Users/runner/work/qemu/qemu/include/system/hvf.h:45:5: error: type name requires a specifier or qualifier > QTAILQ_ENTRY(hvf_sw_breakpoint) entry; > ^ > /Users/runner/work/qemu/qemu/include/system/hvf.h:45:18: error: a parameter list without types is only allowed in a function definition > QTAILQ_ENTRY(hvf_sw_breakpoint) entry; > ^ > /Users/runner/work/qemu/qemu/include/system/hvf.h:45:36: error: expected ';' at end of declaration list > QTAILQ_ENTRY(hvf_sw_breakpoint) entry; > > Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > include/system/hvf.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/include/system/hvf.h b/include/system/hvf.h > index 7b45a2e1988..a9a502f0c8f 100644 > --- a/include/system/hvf.h > +++ b/include/system/hvf.h > @@ -17,6 +17,7 @@ > #include "qemu/queue.h" > #include "exec/vaddr.h" ^^^^^^^^^^^^ Since commit 0af34b1dacc this patch isn't needed anymore. (no need to respin as it can simply be skipped). > #include "qom/object.h" > +#include "exec/vaddr.h" > > #ifdef COMPILING_PER_TARGET > # ifdef CONFIG_HVF ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v8 03/48] meson: add common libs for target and target_system 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 01/48] target/arm: Replace target_ulong -> vaddr for HWBreakpoint Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 02/48] include/system/hvf: missing vaddr include Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 04/48] target/arm: move kvm stubs and remove CONFIG_KVM from kvm_arm.h Pierrick Bouvier ` (44 subsequent siblings) 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Following what we did for hw/, we need target specific common libraries for target. We need 2 different libraries: - code common to a base architecture - system code common to a base architecture For user code, it can stay compiled per target for now. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- meson.build | 78 +++++++++++++++++++++++++++++++++++++++++------------ 1 file changed, 61 insertions(+), 17 deletions(-) diff --git a/meson.build b/meson.build index bbcba3a84a1..bdcde9746c1 100644 --- a/meson.build +++ b/meson.build @@ -3706,6 +3706,8 @@ target_arch = {} target_system_arch = {} target_user_arch = {} hw_common_arch = {} +target_common_arch = {} +target_common_system_arch = {} # NOTE: the trace/ subdirectory needs the qapi_trace_events variable # that is filled in by qapi/. @@ -4111,29 +4113,59 @@ common_all = static_library('common', # construct common libraries per base architecture hw_common_arch_libs = {} +target_common_arch_libs = {} +target_common_system_arch_libs = {} foreach target : target_dirs config_target = config_target_mak[target] target_base_arch = config_target['TARGET_BASE_ARCH'] + target_inc = [include_directories('target' / target_base_arch)] + inc = [common_user_inc + target_inc] - # check if already generated - if target_base_arch in hw_common_arch_libs - continue - endif + # prevent common code to access cpu compile time definition, + # but still allow access to cpu.h + target_c_args = ['-DCPU_DEFS_H'] + target_system_c_args = target_c_args + ['-DCOMPILING_SYSTEM_VS_USER', '-DCONFIG_SOFTMMU'] if target_base_arch in hw_common_arch - target_inc = [include_directories('target' / target_base_arch)] - src = hw_common_arch[target_base_arch] - lib = static_library( - 'hw_' + target_base_arch, - build_by_default: false, - sources: src.all_sources() + genh, - include_directories: common_user_inc + target_inc, - implicit_include_directories: false, - # prevent common code to access cpu compile time - # definition, but still allow access to cpu.h - c_args: ['-DCPU_DEFS_H', '-DCOMPILING_SYSTEM_VS_USER', '-DCONFIG_SOFTMMU'], - dependencies: src.all_dependencies()) - hw_common_arch_libs += {target_base_arch: lib} + if target_base_arch not in hw_common_arch_libs + src = hw_common_arch[target_base_arch] + lib = static_library( + 'hw_' + target_base_arch, + build_by_default: false, + sources: src.all_sources() + genh, + include_directories: inc, + c_args: target_system_c_args, + dependencies: src.all_dependencies()) + hw_common_arch_libs += {target_base_arch: lib} + endif + endif + + if target_base_arch in target_common_arch + if target_base_arch not in target_common_arch_libs + src = target_common_arch[target_base_arch] + lib = static_library( + 'target_' + target_base_arch, + build_by_default: false, + sources: src.all_sources() + genh, + include_directories: inc, + c_args: target_c_args, + dependencies: src.all_dependencies()) + target_common_arch_libs += {target_base_arch: lib} + endif + endif + + if target_base_arch in target_common_system_arch + if target_base_arch not in target_common_system_arch_libs + src = target_common_system_arch[target_base_arch] + lib = static_library( + 'target_system_' + target_base_arch, + build_by_default: false, + sources: src.all_sources() + genh, + include_directories: inc, + c_args: target_system_c_args, + dependencies: src.all_dependencies()) + target_common_system_arch_libs += {target_base_arch: lib} + endif endif endforeach @@ -4306,12 +4338,24 @@ foreach target : target_dirs target_common = common_ss.apply(config_target, strict: false) objects = [common_all.extract_objects(target_common.sources())] arch_deps += target_common.dependencies() + if target_base_arch in target_common_arch_libs + src = target_common_arch[target_base_arch].apply(config_target, strict: false) + lib = target_common_arch_libs[target_base_arch] + objects += lib.extract_objects(src.sources()) + arch_deps += src.dependencies() + endif if target_type == 'system' and target_base_arch in hw_common_arch_libs src = hw_common_arch[target_base_arch].apply(config_target, strict: false) lib = hw_common_arch_libs[target_base_arch] objects += lib.extract_objects(src.sources()) arch_deps += src.dependencies() endif + if target_type == 'system' and target_base_arch in target_common_system_arch_libs + src = target_common_system_arch[target_base_arch].apply(config_target, strict: false) + lib = target_common_system_arch_libs[target_base_arch] + objects += lib.extract_objects(src.sources()) + arch_deps += src.dependencies() + endif target_specific = specific_ss.apply(config_target, strict: false) arch_srcs += target_specific.sources() -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v8 04/48] target/arm: move kvm stubs and remove CONFIG_KVM from kvm_arm.h 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (2 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 03/48] meson: add common libs for target and target_system Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-13 9:58 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 05/48] target/arm/kvm-stub: add kvm_arm_reset_vcpu stub Pierrick Bouvier ` (43 subsequent siblings) 47 siblings, 1 reply; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Add a forward decl for struct kvm_vcpu_init to avoid pulling all kvm headers. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/kvm_arm.h | 83 +------------------------------------------ target/arm/kvm-stub.c | 77 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+), 82 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 5f17fc2f3d5..5bf5d56648f 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -94,7 +94,7 @@ void kvm_arm_cpu_post_load(ARMCPU *cpu); */ void kvm_arm_reset_vcpu(ARMCPU *cpu); -#ifdef CONFIG_KVM +struct kvm_vcpu_init; /** * kvm_arm_create_scratch_host_vcpu: * @fdarray: filled in with kvmfd, vmfd, cpufd file descriptors in that order @@ -216,85 +216,4 @@ int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level); void kvm_arm_enable_mte(Object *cpuobj, Error **errp); -#else - -/* - * It's safe to call these functions without KVM support. - * They should either do nothing or return "not supported". - */ -static inline bool kvm_arm_aarch32_supported(void) -{ - return false; -} - -static inline bool kvm_arm_pmu_supported(void) -{ - return false; -} - -static inline bool kvm_arm_sve_supported(void) -{ - return false; -} - -static inline bool kvm_arm_mte_supported(void) -{ - return false; -} - -/* - * These functions should never actually be called without KVM support. - */ -static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) -{ - g_assert_not_reached(); -} - -static inline void kvm_arm_add_vcpu_properties(ARMCPU *cpu) -{ - g_assert_not_reached(); -} - -static inline int kvm_arm_get_max_vm_ipa_size(MachineState *ms, bool *fixed_ipa) -{ - g_assert_not_reached(); -} - -static inline int kvm_arm_vgic_probe(void) -{ - g_assert_not_reached(); -} - -static inline void kvm_arm_pmu_set_irq(ARMCPU *cpu, int irq) -{ - g_assert_not_reached(); -} - -static inline void kvm_arm_pmu_init(ARMCPU *cpu) -{ - g_assert_not_reached(); -} - -static inline void kvm_arm_pvtime_init(ARMCPU *cpu, uint64_t ipa) -{ - g_assert_not_reached(); -} - -static inline void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp) -{ - g_assert_not_reached(); -} - -static inline uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu) -{ - g_assert_not_reached(); -} - -static inline void kvm_arm_enable_mte(Object *cpuobj, Error **errp) -{ - g_assert_not_reached(); -} - -#endif - #endif diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c index 965a486b320..2b73d0598c1 100644 --- a/target/arm/kvm-stub.c +++ b/target/arm/kvm-stub.c @@ -22,3 +22,80 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level) { g_assert_not_reached(); } + +/* + * It's safe to call these functions without KVM support. + * They should either do nothing or return "not supported". + */ +bool kvm_arm_aarch32_supported(void) +{ + return false; +} + +bool kvm_arm_pmu_supported(void) +{ + return false; +} + +bool kvm_arm_sve_supported(void) +{ + return false; +} + +bool kvm_arm_mte_supported(void) +{ + return false; +} + +/* + * These functions should never actually be called without KVM support. + */ +void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) +{ + g_assert_not_reached(); +} + +void kvm_arm_add_vcpu_properties(ARMCPU *cpu) +{ + g_assert_not_reached(); +} + +int kvm_arm_get_max_vm_ipa_size(MachineState *ms, bool *fixed_ipa) +{ + g_assert_not_reached(); +} + +int kvm_arm_vgic_probe(void) +{ + g_assert_not_reached(); +} + +void kvm_arm_pmu_set_irq(ARMCPU *cpu, int irq) +{ + g_assert_not_reached(); +} + +void kvm_arm_pmu_init(ARMCPU *cpu) +{ + g_assert_not_reached(); +} + +void kvm_arm_pvtime_init(ARMCPU *cpu, uint64_t ipa) +{ + g_assert_not_reached(); +} + +void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp) +{ + g_assert_not_reached(); +} + +uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu) +{ + g_assert_not_reached(); +} + +void kvm_arm_enable_mte(Object *cpuobj, Error **errp) +{ + g_assert_not_reached(); +} -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v8 04/48] target/arm: move kvm stubs and remove CONFIG_KVM from kvm_arm.h 2025-05-12 18:04 ` [PATCH v8 04/48] target/arm: move kvm stubs and remove CONFIG_KVM from kvm_arm.h Pierrick Bouvier @ 2025-05-13 9:58 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 71+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-13 9:58 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson On 12/5/25 20:04, Pierrick Bouvier wrote: > Add a forward decl for struct kvm_vcpu_init to avoid pulling all kvm > headers. > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/kvm_arm.h | 83 +------------------------------------------ > target/arm/kvm-stub.c | 77 +++++++++++++++++++++++++++++++++++++++ > 2 files changed, 78 insertions(+), 82 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v8 05/48] target/arm/kvm-stub: add kvm_arm_reset_vcpu stub 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (3 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 04/48] target/arm: move kvm stubs and remove CONFIG_KVM from kvm_arm.h Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-13 10:00 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 06/48] target/arm/cpu: move arm_cpu_kvm_set_irq to kvm.c Pierrick Bouvier ` (42 subsequent siblings) 47 siblings, 1 reply; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Needed in target/arm/cpu.c once kvm is possible. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/kvm-stub.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c index 2b73d0598c1..e34d3f5e6b4 100644 --- a/target/arm/kvm-stub.c +++ b/target/arm/kvm-stub.c @@ -99,3 +99,8 @@ void kvm_arm_enable_mte(Object *cpuobj, Error **errp) { g_assert_not_reached(); } + +void kvm_arm_reset_vcpu(ARMCPU *cpu) +{ + g_assert_not_reached(); +} -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v8 05/48] target/arm/kvm-stub: add kvm_arm_reset_vcpu stub 2025-05-12 18:04 ` [PATCH v8 05/48] target/arm/kvm-stub: add kvm_arm_reset_vcpu stub Pierrick Bouvier @ 2025-05-13 10:00 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 71+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-13 10:00 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson On 12/5/25 20:04, Pierrick Bouvier wrote: > Needed in target/arm/cpu.c once kvm is possible. > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/kvm-stub.c | 5 +++++ > 1 file changed, 5 insertions(+) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v8 06/48] target/arm/cpu: move arm_cpu_kvm_set_irq to kvm.c 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (4 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 05/48] target/arm/kvm-stub: add kvm_arm_reset_vcpu stub Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 07/48] target/arm/cpu: remove TARGET_BIG_ENDIAN dependency Pierrick Bouvier ` (41 subsequent siblings) 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Allow to get rid of CONFIG_KVM in target/arm/cpu.c Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/kvm_arm.h | 2 ++ target/arm/cpu.c | 31 ------------------------------- target/arm/kvm-stub.c | 5 +++++ target/arm/kvm.c | 29 +++++++++++++++++++++++++++++ 4 files changed, 36 insertions(+), 31 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 5bf5d56648f..b638e09a687 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -216,4 +216,6 @@ int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level); void kvm_arm_enable_mte(Object *cpuobj, Error **errp); +void arm_cpu_kvm_set_irq(void *arm_cpu, int irq, int level); + #endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 45cb6fd7eed..d062829ec14 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1098,37 +1098,6 @@ static void arm_cpu_set_irq(void *opaque, int irq, int level) } } -static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) -{ -#ifdef CONFIG_KVM - ARMCPU *cpu = opaque; - CPUARMState *env = &cpu->env; - CPUState *cs = CPU(cpu); - uint32_t linestate_bit; - int irq_id; - - switch (irq) { - case ARM_CPU_IRQ: - irq_id = KVM_ARM_IRQ_CPU_IRQ; - linestate_bit = CPU_INTERRUPT_HARD; - break; - case ARM_CPU_FIQ: - irq_id = KVM_ARM_IRQ_CPU_FIQ; - linestate_bit = CPU_INTERRUPT_FIQ; - break; - default: - g_assert_not_reached(); - } - - if (level) { - env->irq_line_state |= linestate_bit; - } else { - env->irq_line_state &= ~linestate_bit; - } - kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); -#endif -} - static bool arm_cpu_virtio_is_big_endian(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c index e34d3f5e6b4..4806365cdc5 100644 --- a/target/arm/kvm-stub.c +++ b/target/arm/kvm-stub.c @@ -104,3 +104,8 @@ void kvm_arm_reset_vcpu(ARMCPU *cpu) { g_assert_not_reached(); } + +void arm_cpu_kvm_set_irq(void *arm_cpu, int irq, int level) +{ + g_assert_not_reached(); +} diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 9c62d12b233..b6c39ca61fa 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -2429,3 +2429,32 @@ void kvm_arm_enable_mte(Object *cpuobj, Error **errp) cpu->kvm_mte = true; } } + +void arm_cpu_kvm_set_irq(void *arm_cpu, int irq, int level) +{ + ARMCPU *cpu = arm_cpu; + CPUARMState *env = &cpu->env; + CPUState *cs = CPU(cpu); + uint32_t linestate_bit; + int irq_id; + + switch (irq) { + case ARM_CPU_IRQ: + irq_id = KVM_ARM_IRQ_CPU_IRQ; + linestate_bit = CPU_INTERRUPT_HARD; + break; + case ARM_CPU_FIQ: + irq_id = KVM_ARM_IRQ_CPU_FIQ; + linestate_bit = CPU_INTERRUPT_FIQ; + break; + default: + g_assert_not_reached(); + } + + if (level) { + env->irq_line_state |= linestate_bit; + } else { + env->irq_line_state &= ~linestate_bit; + } + kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); +} -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v8 07/48] target/arm/cpu: remove TARGET_BIG_ENDIAN dependency 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (5 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 06/48] target/arm/cpu: move arm_cpu_kvm_set_irq to kvm.c Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 08/48] target/arm/cpu: remove TARGET_AARCH64 around aarch64_cpu_dump_state common Pierrick Bouvier ` (40 subsequent siblings) 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d062829ec14..b0eb02c88ba 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -23,6 +23,7 @@ #include "qemu/timer.h" #include "qemu/log.h" #include "exec/page-vary.h" +#include "exec/tswap.h" #include "target/arm/idau.h" #include "qemu/module.h" #include "qapi/error.h" @@ -1171,7 +1172,7 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) info->endian = BFD_ENDIAN_LITTLE; if (bswap_code(sctlr_b)) { - info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; + info->endian = target_big_endian() ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; } info->flags &= ~INSN_ARM_BE32; #ifndef CONFIG_USER_ONLY -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v8 08/48] target/arm/cpu: remove TARGET_AARCH64 around aarch64_cpu_dump_state common 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (6 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 07/48] target/arm/cpu: remove TARGET_BIG_ENDIAN dependency Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 09/48] target/arm/cpu: remove TARGET_AARCH64 in arm_cpu_finalize_features Pierrick Bouvier ` (39 subsequent siblings) 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Call is guarded by is_a64(env), so it's safe to expose without needing to assert anything. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/cpu.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b0eb02c88ba..b97746faa87 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1182,8 +1182,6 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) #endif } -#ifdef TARGET_AARCH64 - static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) { ARMCPU *cpu = ARM_CPU(cs); @@ -1341,15 +1339,6 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) } } -#else - -static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) -{ - g_assert_not_reached(); -} - -#endif - static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) { ARMCPU *cpu = ARM_CPU(cs); -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v8 09/48] target/arm/cpu: remove TARGET_AARCH64 in arm_cpu_finalize_features 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (7 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 08/48] target/arm/cpu: remove TARGET_AARCH64 around aarch64_cpu_dump_state common Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 10/48] target/arm/cpu: compile file twice (user, system) only Pierrick Bouvier ` (38 subsequent siblings) 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Need to stub cpu64 finalize functions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/cpu.c | 2 -- target/arm/cpu32-stubs.c | 26 ++++++++++++++++++++++++++ target/arm/meson.build | 11 +++++++---- 3 files changed, 33 insertions(+), 6 deletions(-) create mode 100644 target/arm/cpu32-stubs.c diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b97746faa87..a604e4ccac8 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1877,7 +1877,6 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) { Error *local_err = NULL; -#ifdef TARGET_AARCH64 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { arm_cpu_sve_finalize(cpu, &local_err); if (local_err != NULL) { @@ -1913,7 +1912,6 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) return; } } -#endif if (kvm_enabled()) { kvm_arm_steal_time_finalize(cpu, &local_err); diff --git a/target/arm/cpu32-stubs.c b/target/arm/cpu32-stubs.c new file mode 100644 index 00000000000..81be44d8462 --- /dev/null +++ b/target/arm/cpu32-stubs.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include "qemu/osdep.h" +#include "target/arm/cpu.h" +#include "target/arm/internals.h" +#include <glib.h> + +void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) +{ + g_assert_not_reached(); +} + +void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) +{ + g_assert_not_reached(); +} + +void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) +{ + g_assert_not_reached(); +} + +void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) +{ + g_assert_not_reached(); +} diff --git a/target/arm/meson.build b/target/arm/meson.build index 3065081d241..c39ddc4427b 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -11,10 +11,13 @@ arm_ss.add(zlib) arm_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c'), if_false: files('kvm-stub.c')) arm_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) -arm_ss.add(when: 'TARGET_AARCH64', if_true: files( - 'cpu64.c', - 'gdbstub64.c', -)) +arm_ss.add(when: 'TARGET_AARCH64', + if_true: files( + 'cpu64.c', + 'gdbstub64.c'), + if_false: files( + 'cpu32-stubs.c'), +) arm_system_ss = ss.source_set() arm_system_ss.add(files( -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v8 10/48] target/arm/cpu: compile file twice (user, system) only 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (8 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 09/48] target/arm/cpu: remove TARGET_AARCH64 in arm_cpu_finalize_features Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 11/48] target/arm/cpu32-stubs.c: compile file twice (user, system) Pierrick Bouvier ` (37 subsequent siblings) 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/meson.build | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index c39ddc4427b..89e305eb56a 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -1,6 +1,6 @@ arm_ss = ss.source_set() +arm_common_ss = ss.source_set() arm_ss.add(files( - 'cpu.c', 'debug_helper.c', 'gdbstub.c', 'helper.c', @@ -20,6 +20,7 @@ arm_ss.add(when: 'TARGET_AARCH64', ) arm_system_ss = ss.source_set() +arm_common_system_ss = ss.source_set() arm_system_ss.add(files( 'arch_dump.c', 'arm-powerctl.c', @@ -30,6 +31,9 @@ arm_system_ss.add(files( )) arm_user_ss = ss.source_set() +arm_user_ss.add(files('cpu.c')) + +arm_common_system_ss.add(files('cpu.c'), capstone) subdir('hvf') @@ -42,3 +46,5 @@ endif target_arch += {'arm': arm_ss} target_system_arch += {'arm': arm_system_ss} target_user_arch += {'arm': arm_user_ss} +target_common_arch += {'arm': arm_common_ss} +target_common_system_arch += {'arm': arm_common_system_ss} -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v8 11/48] target/arm/cpu32-stubs.c: compile file twice (user, system) 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (9 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 10/48] target/arm/cpu: compile file twice (user, system) only Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 12/48] tcg: add vaddr type for helpers Pierrick Bouvier ` (36 subsequent siblings) 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier It could be squashed with commit introducing it, but I would prefer to introduce target/arm/cpu.c first. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/meson.build | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 89e305eb56a..de214fe5d56 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -11,13 +11,9 @@ arm_ss.add(zlib) arm_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c'), if_false: files('kvm-stub.c')) arm_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) -arm_ss.add(when: 'TARGET_AARCH64', - if_true: files( - 'cpu64.c', - 'gdbstub64.c'), - if_false: files( - 'cpu32-stubs.c'), -) +arm_ss.add(when: 'TARGET_AARCH64', if_true: files( + 'cpu64.c', + 'gdbstub64.c')) arm_system_ss = ss.source_set() arm_common_system_ss = ss.source_set() @@ -32,8 +28,12 @@ arm_system_ss.add(files( arm_user_ss = ss.source_set() arm_user_ss.add(files('cpu.c')) +arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files( + 'cpu32-stubs.c')) arm_common_system_ss.add(files('cpu.c'), capstone) +arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files( + 'cpu32-stubs.c')) subdir('hvf') -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v8 12/48] tcg: add vaddr type for helpers 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (10 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 11/48] target/arm/cpu32-stubs.c: compile file twice (user, system) Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-13 10:03 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 13/48] target/arm/helper: use vaddr instead of target_ulong for exception_pc_alignment Pierrick Bouvier ` (35 subsequent siblings) 47 siblings, 1 reply; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Defined as an alias of i32/i64 depending on host pointer size. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- include/tcg/tcg-op-common.h | 1 + include/tcg/tcg.h | 14 ++++++++++++++ include/exec/helper-head.h.inc | 11 +++++++++++ tcg/tcg.c | 5 +++++ 4 files changed, 31 insertions(+) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index b439bdb385a..e1071adebf2 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -14,6 +14,7 @@ TCGv_i32 tcg_constant_i32(int32_t val); TCGv_i64 tcg_constant_i64(int64_t val); +TCGv_vaddr tcg_constant_vaddr(uintptr_t val); TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val); TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val); diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index a8c00c72cc8..3fa5a7aed2c 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -189,6 +189,7 @@ typedef tcg_target_ulong TCGArg; * TCGv_i64 : 64 bit integer type * TCGv_i128 : 128 bit integer type * TCGv_ptr : a host pointer type + * TCGv_vaddr: an integer type wide enough to hold a target pointer type * TCGv_vec : a host vector type; the exact size is not exposed to the CPU front-end code. * TCGv : an integer type the same size as target_ulong @@ -217,6 +218,14 @@ typedef struct TCGv_ptr_d *TCGv_ptr; typedef struct TCGv_vec_d *TCGv_vec; typedef TCGv_ptr TCGv_env; +#if __SIZEOF_POINTER__ == 4 +typedef TCGv_i32 TCGv_vaddr; +#elif __SIZEOF_POINTER__ == 8 +typedef TCGv_i64 TCGv_vaddr; +#else +# error "sizeof pointer is different from {4,8}" +#endif /* __SIZEOF_POINTER__ */ + /* call flags */ /* Helper does not read globals (either directly or through an exception). It implies TCG_CALL_NO_WRITE_GLOBALS. */ @@ -577,6 +586,11 @@ static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t) return (TCGv_ptr)temp_tcgv_i32(t); } +static inline TCGv_vaddr temp_tcgv_vaddr(TCGTemp *t) +{ + return (TCGv_vaddr)temp_tcgv_i32(t); +} + static inline TCGv_vec temp_tcgv_vec(TCGTemp *t) { return (TCGv_vec)temp_tcgv_i32(t); diff --git a/include/exec/helper-head.h.inc b/include/exec/helper-head.h.inc index bce5db06ef3..5b248fd7138 100644 --- a/include/exec/helper-head.h.inc +++ b/include/exec/helper-head.h.inc @@ -58,6 +58,17 @@ # define dh_ctype_tl target_ulong #endif /* COMPILING_PER_TARGET */ +#if __SIZEOF_POINTER__ == 4 +# define dh_alias_vaddr i32 +# define dh_typecode_vaddr dh_typecode_i32 +#elif __SIZEOF_POINTER__ == 8 +# define dh_alias_vaddr i64 +# define dh_typecode_vaddr dh_typecode_i64 +#else +# error "sizeof pointer is different from {4,8}" +#endif /* __SIZEOF_POINTER__ */ +# define dh_ctype_vaddr uintptr_t + /* We can't use glue() here because it falls foul of C preprocessor recursive expansion rules. */ #define dh_retvar_decl0_void void diff --git a/tcg/tcg.c b/tcg/tcg.c index 648333a9fb7..ae27a2607df 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2367,6 +2367,11 @@ TCGv_i64 tcg_constant_i64(int64_t val) return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64, val)); } +TCGv_vaddr tcg_constant_vaddr(uintptr_t val) +{ + return temp_tcgv_vaddr(tcg_constant_internal(TCG_TYPE_PTR, val)); +} + TCGv_ptr tcg_constant_ptr_int(intptr_t val) { return temp_tcgv_ptr(tcg_constant_internal(TCG_TYPE_PTR, val)); -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v8 12/48] tcg: add vaddr type for helpers 2025-05-12 18:04 ` [PATCH v8 12/48] tcg: add vaddr type for helpers Pierrick Bouvier @ 2025-05-13 10:03 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 71+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-13 10:03 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson On 12/5/25 20:04, Pierrick Bouvier wrote: > Defined as an alias of i32/i64 depending on host pointer size. > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > include/tcg/tcg-op-common.h | 1 + > include/tcg/tcg.h | 14 ++++++++++++++ > include/exec/helper-head.h.inc | 11 +++++++++++ > tcg/tcg.c | 5 +++++ > 4 files changed, 31 insertions(+) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v8 13/48] target/arm/helper: use vaddr instead of target_ulong for exception_pc_alignment 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (11 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 12/48] tcg: add vaddr type for helpers Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-13 10:03 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 14/48] target/arm/helper: use vaddr instead of target_ulong for probe_access Pierrick Bouvier ` (34 subsequent siblings) 47 siblings, 1 reply; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/helper.h | 2 +- target/arm/tcg/tlb_helper.c | 2 +- target/arm/tcg/translate-a64.c | 2 +- target/arm/tcg/translate.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 09075058391..95b9211c6f4 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -49,7 +49,7 @@ DEF_HELPER_3(exception_with_syndrome, noreturn, env, i32, i32) DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32) DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) DEF_HELPER_2(exception_swstep, noreturn, env, i32) -DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) +DEF_HELPER_2(exception_pc_alignment, noreturn, env, vaddr) DEF_HELPER_1(setend, void, env) DEF_HELPER_2(wfi, void, env, i32) DEF_HELPER_1(wfe, void, env) diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 5ea4d6590f2..d9e6c827d43 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -276,7 +276,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); } -void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc) +void helper_exception_pc_alignment(CPUARMState *env, vaddr pc) { ARMMMUFaultInfo fi = { .type = ARMFault_Alignment }; int target_el = exception_target_el(env); diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 52cf47e775f..ac80f572a2d 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -10242,7 +10242,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) * start of the TB. */ assert(s->base.num_insns == 1); - gen_helper_exception_pc_alignment(tcg_env, tcg_constant_tl(pc)); + gen_helper_exception_pc_alignment(tcg_env, tcg_constant_vaddr(pc)); s->base.is_jmp = DISAS_NORETURN; s->base.pc_next = QEMU_ALIGN_UP(pc, 4); return; diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index e773ab72685..9962f43b1d0 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -7791,7 +7791,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) * be possible after an indirect branch, at the start of the TB. */ assert(dc->base.num_insns == 1); - gen_helper_exception_pc_alignment(tcg_env, tcg_constant_tl(pc)); + gen_helper_exception_pc_alignment(tcg_env, tcg_constant_vaddr(pc)); dc->base.is_jmp = DISAS_NORETURN; dc->base.pc_next = QEMU_ALIGN_UP(pc, 4); return; -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v8 13/48] target/arm/helper: use vaddr instead of target_ulong for exception_pc_alignment 2025-05-12 18:04 ` [PATCH v8 13/48] target/arm/helper: use vaddr instead of target_ulong for exception_pc_alignment Pierrick Bouvier @ 2025-05-13 10:03 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 71+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-13 10:03 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson On 12/5/25 20:04, Pierrick Bouvier wrote: > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/helper.h | 2 +- > target/arm/tcg/tlb_helper.c | 2 +- > target/arm/tcg/translate-a64.c | 2 +- > target/arm/tcg/translate.c | 2 +- > 4 files changed, 4 insertions(+), 4 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v8 14/48] target/arm/helper: use vaddr instead of target_ulong for probe_access 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (12 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 13/48] target/arm/helper: use vaddr instead of target_ulong for exception_pc_alignment Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-13 10:04 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 15/48] target/arm/helper: extract common helpers Pierrick Bouvier ` (33 subsequent siblings) 47 siblings, 1 reply; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/helper.h | 2 +- target/arm/tcg/op_helper.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 95b9211c6f4..0a4fc90fa8b 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -104,7 +104,7 @@ DEF_HELPER_FLAGS_1(rebuild_hflags_a32_newel, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int) DEF_HELPER_FLAGS_2(rebuild_hflags_a64, TCG_CALL_NO_RWG, void, env, int) -DEF_HELPER_FLAGS_5(probe_access, TCG_CALL_NO_WG, void, env, tl, i32, i32, i32) +DEF_HELPER_FLAGS_5(probe_access, TCG_CALL_NO_WG, void, env, vaddr, i32, i32, i32) DEF_HELPER_1(vfp_get_fpscr, i32, env) DEF_HELPER_2(vfp_set_fpscr, void, env, i32) diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index dc3f83c37dc..575e566280b 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -1222,7 +1222,7 @@ uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i) } } -void HELPER(probe_access)(CPUARMState *env, target_ulong ptr, +void HELPER(probe_access)(CPUARMState *env, vaddr ptr, uint32_t access_type, uint32_t mmu_idx, uint32_t size) { -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v8 14/48] target/arm/helper: use vaddr instead of target_ulong for probe_access 2025-05-12 18:04 ` [PATCH v8 14/48] target/arm/helper: use vaddr instead of target_ulong for probe_access Pierrick Bouvier @ 2025-05-13 10:04 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 71+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-13 10:04 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson On 12/5/25 20:04, Pierrick Bouvier wrote: > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/helper.h | 2 +- > target/arm/tcg/op_helper.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v8 15/48] target/arm/helper: extract common helpers 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (13 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 14/48] target/arm/helper: use vaddr instead of target_ulong for probe_access Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 16/48] target/arm/debug_helper: only include " Pierrick Bouvier ` (32 subsequent siblings) 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Allow later commits to include only the "new" tcg/helper.h, thus preventing to pull aarch64 helpers (+ target/arm/helper.h contains a ifdef TARGET_AARCH64). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/helper.h | 1152 +------------------------------------- target/arm/tcg/helper.h | 1153 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 1155 insertions(+), 1150 deletions(-) create mode 100644 target/arm/tcg/helper.h diff --git a/target/arm/helper.h b/target/arm/helper.h index 0a4fc90fa8b..f340a49a28a 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -1,1154 +1,6 @@ -DEF_HELPER_FLAGS_1(sxtb16, TCG_CALL_NO_RWG_SE, i32, i32) -DEF_HELPER_FLAGS_1(uxtb16, TCG_CALL_NO_RWG_SE, i32, i32) +/* SPDX-License-Identifier: GPL-2.0-or-later */ -DEF_HELPER_3(add_setq, i32, env, i32, i32) -DEF_HELPER_3(add_saturate, i32, env, i32, i32) -DEF_HELPER_3(sub_saturate, i32, env, i32, i32) -DEF_HELPER_3(add_usaturate, i32, env, i32, i32) -DEF_HELPER_3(sub_usaturate, i32, env, i32, i32) -DEF_HELPER_FLAGS_3(sdiv, TCG_CALL_NO_RWG, s32, env, s32, s32) -DEF_HELPER_FLAGS_3(udiv, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_1(rbit, TCG_CALL_NO_RWG_SE, i32, i32) - -#define PAS_OP(pfx) \ - DEF_HELPER_3(pfx ## add8, i32, i32, i32, ptr) \ - DEF_HELPER_3(pfx ## sub8, i32, i32, i32, ptr) \ - DEF_HELPER_3(pfx ## sub16, i32, i32, i32, ptr) \ - DEF_HELPER_3(pfx ## add16, i32, i32, i32, ptr) \ - DEF_HELPER_3(pfx ## addsubx, i32, i32, i32, ptr) \ - DEF_HELPER_3(pfx ## subaddx, i32, i32, i32, ptr) - -PAS_OP(s) -PAS_OP(u) -#undef PAS_OP - -#define PAS_OP(pfx) \ - DEF_HELPER_2(pfx ## add8, i32, i32, i32) \ - DEF_HELPER_2(pfx ## sub8, i32, i32, i32) \ - DEF_HELPER_2(pfx ## sub16, i32, i32, i32) \ - DEF_HELPER_2(pfx ## add16, i32, i32, i32) \ - DEF_HELPER_2(pfx ## addsubx, i32, i32, i32) \ - DEF_HELPER_2(pfx ## subaddx, i32, i32, i32) -PAS_OP(q) -PAS_OP(sh) -PAS_OP(uq) -PAS_OP(uh) -#undef PAS_OP - -DEF_HELPER_3(ssat, i32, env, i32, i32) -DEF_HELPER_3(usat, i32, env, i32, i32) -DEF_HELPER_3(ssat16, i32, env, i32, i32) -DEF_HELPER_3(usat16, i32, env, i32, i32) - -DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32) - -DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, - i32, i32, i32, i32) -DEF_HELPER_2(exception_internal, noreturn, env, i32) -DEF_HELPER_3(exception_with_syndrome, noreturn, env, i32, i32) -DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32) -DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) -DEF_HELPER_2(exception_swstep, noreturn, env, i32) -DEF_HELPER_2(exception_pc_alignment, noreturn, env, vaddr) -DEF_HELPER_1(setend, void, env) -DEF_HELPER_2(wfi, void, env, i32) -DEF_HELPER_1(wfe, void, env) -DEF_HELPER_2(wfit, void, env, i64) -DEF_HELPER_1(yield, void, env) -DEF_HELPER_1(pre_hvc, void, env) -DEF_HELPER_2(pre_smc, void, env, i32) -DEF_HELPER_1(vesb, void, env) - -DEF_HELPER_3(cpsr_write, void, env, i32, i32) -DEF_HELPER_2(cpsr_write_eret, void, env, i32) -DEF_HELPER_1(cpsr_read, i32, env) - -DEF_HELPER_3(v7m_msr, void, env, i32, i32) -DEF_HELPER_2(v7m_mrs, i32, env, i32) - -DEF_HELPER_2(v7m_bxns, void, env, i32) -DEF_HELPER_2(v7m_blxns, void, env, i32) - -DEF_HELPER_3(v7m_tt, i32, env, i32, i32) - -DEF_HELPER_1(v7m_preserve_fp_state, void, env) - -DEF_HELPER_2(v7m_vlstm, void, env, i32) -DEF_HELPER_2(v7m_vlldm, void, env, i32) - -DEF_HELPER_2(v8m_stackcheck, void, env, i32) - -DEF_HELPER_FLAGS_2(check_bxj_trap, TCG_CALL_NO_WG, void, env, i32) - -DEF_HELPER_4(access_check_cp_reg, cptr, env, i32, i32, i32) -DEF_HELPER_FLAGS_2(lookup_cp_reg, TCG_CALL_NO_RWG_SE, cptr, env, i32) -DEF_HELPER_FLAGS_2(tidcp_el0, TCG_CALL_NO_WG, void, env, i32) -DEF_HELPER_FLAGS_2(tidcp_el1, TCG_CALL_NO_WG, void, env, i32) -DEF_HELPER_3(set_cp_reg, void, env, cptr, i32) -DEF_HELPER_2(get_cp_reg, i32, env, cptr) -DEF_HELPER_3(set_cp_reg64, void, env, cptr, i64) -DEF_HELPER_2(get_cp_reg64, i64, env, cptr) - -DEF_HELPER_2(get_r13_banked, i32, env, i32) -DEF_HELPER_3(set_r13_banked, void, env, i32, i32) - -DEF_HELPER_3(mrs_banked, i32, env, i32, i32) -DEF_HELPER_4(msr_banked, void, env, i32, i32, i32) - -DEF_HELPER_2(get_user_reg, i32, env, i32) -DEF_HELPER_3(set_user_reg, void, env, i32, i32) - -DEF_HELPER_FLAGS_1(rebuild_hflags_m32_newel, TCG_CALL_NO_RWG, void, env) -DEF_HELPER_FLAGS_2(rebuild_hflags_m32, TCG_CALL_NO_RWG, void, env, int) -DEF_HELPER_FLAGS_1(rebuild_hflags_a32_newel, TCG_CALL_NO_RWG, void, env) -DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int) -DEF_HELPER_FLAGS_2(rebuild_hflags_a64, TCG_CALL_NO_RWG, void, env, int) - -DEF_HELPER_FLAGS_5(probe_access, TCG_CALL_NO_WG, void, env, vaddr, i32, i32, i32) - -DEF_HELPER_1(vfp_get_fpscr, i32, env) -DEF_HELPER_2(vfp_set_fpscr, void, env, i32) - -DEF_HELPER_3(vfp_addh, f16, f16, f16, fpst) -DEF_HELPER_3(vfp_adds, f32, f32, f32, fpst) -DEF_HELPER_3(vfp_addd, f64, f64, f64, fpst) -DEF_HELPER_3(vfp_subh, f16, f16, f16, fpst) -DEF_HELPER_3(vfp_subs, f32, f32, f32, fpst) -DEF_HELPER_3(vfp_subd, f64, f64, f64, fpst) -DEF_HELPER_3(vfp_mulh, f16, f16, f16, fpst) -DEF_HELPER_3(vfp_muls, f32, f32, f32, fpst) -DEF_HELPER_3(vfp_muld, f64, f64, f64, fpst) -DEF_HELPER_3(vfp_divh, f16, f16, f16, fpst) -DEF_HELPER_3(vfp_divs, f32, f32, f32, fpst) -DEF_HELPER_3(vfp_divd, f64, f64, f64, fpst) -DEF_HELPER_3(vfp_maxh, f16, f16, f16, fpst) -DEF_HELPER_3(vfp_maxs, f32, f32, f32, fpst) -DEF_HELPER_3(vfp_maxd, f64, f64, f64, fpst) -DEF_HELPER_3(vfp_minh, f16, f16, f16, fpst) -DEF_HELPER_3(vfp_mins, f32, f32, f32, fpst) -DEF_HELPER_3(vfp_mind, f64, f64, f64, fpst) -DEF_HELPER_3(vfp_maxnumh, f16, f16, f16, fpst) -DEF_HELPER_3(vfp_maxnums, f32, f32, f32, fpst) -DEF_HELPER_3(vfp_maxnumd, f64, f64, f64, fpst) -DEF_HELPER_3(vfp_minnumh, f16, f16, f16, fpst) -DEF_HELPER_3(vfp_minnums, f32, f32, f32, fpst) -DEF_HELPER_3(vfp_minnumd, f64, f64, f64, fpst) -DEF_HELPER_2(vfp_sqrth, f16, f16, fpst) -DEF_HELPER_2(vfp_sqrts, f32, f32, fpst) -DEF_HELPER_2(vfp_sqrtd, f64, f64, fpst) -DEF_HELPER_3(vfp_cmph, void, f16, f16, env) -DEF_HELPER_3(vfp_cmps, void, f32, f32, env) -DEF_HELPER_3(vfp_cmpd, void, f64, f64, env) -DEF_HELPER_3(vfp_cmpeh, void, f16, f16, env) -DEF_HELPER_3(vfp_cmpes, void, f32, f32, env) -DEF_HELPER_3(vfp_cmped, void, f64, f64, env) - -DEF_HELPER_2(vfp_fcvtds, f64, f32, fpst) -DEF_HELPER_2(vfp_fcvtsd, f32, f64, fpst) -DEF_HELPER_FLAGS_2(bfcvt, TCG_CALL_NO_RWG, i32, f32, fpst) -DEF_HELPER_FLAGS_2(bfcvt_pair, TCG_CALL_NO_RWG, i32, i64, fpst) - -DEF_HELPER_2(vfp_uitoh, f16, i32, fpst) -DEF_HELPER_2(vfp_uitos, f32, i32, fpst) -DEF_HELPER_2(vfp_uitod, f64, i32, fpst) -DEF_HELPER_2(vfp_sitoh, f16, i32, fpst) -DEF_HELPER_2(vfp_sitos, f32, i32, fpst) -DEF_HELPER_2(vfp_sitod, f64, i32, fpst) - -DEF_HELPER_2(vfp_touih, i32, f16, fpst) -DEF_HELPER_2(vfp_touis, i32, f32, fpst) -DEF_HELPER_2(vfp_touid, i32, f64, fpst) -DEF_HELPER_2(vfp_touizh, i32, f16, fpst) -DEF_HELPER_2(vfp_touizs, i32, f32, fpst) -DEF_HELPER_2(vfp_touizd, i32, f64, fpst) -DEF_HELPER_2(vfp_tosih, s32, f16, fpst) -DEF_HELPER_2(vfp_tosis, s32, f32, fpst) -DEF_HELPER_2(vfp_tosid, s32, f64, fpst) -DEF_HELPER_2(vfp_tosizh, s32, f16, fpst) -DEF_HELPER_2(vfp_tosizs, s32, f32, fpst) -DEF_HELPER_2(vfp_tosizd, s32, f64, fpst) - -DEF_HELPER_3(vfp_toshh_round_to_zero, i32, f16, i32, fpst) -DEF_HELPER_3(vfp_toslh_round_to_zero, i32, f16, i32, fpst) -DEF_HELPER_3(vfp_touhh_round_to_zero, i32, f16, i32, fpst) -DEF_HELPER_3(vfp_toulh_round_to_zero, i32, f16, i32, fpst) -DEF_HELPER_3(vfp_toshs_round_to_zero, i32, f32, i32, fpst) -DEF_HELPER_3(vfp_tosls_round_to_zero, i32, f32, i32, fpst) -DEF_HELPER_3(vfp_touhs_round_to_zero, i32, f32, i32, fpst) -DEF_HELPER_3(vfp_touls_round_to_zero, i32, f32, i32, fpst) -DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_tosqd_round_to_zero, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_touqd_round_to_zero, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_touhh, i32, f16, i32, fpst) -DEF_HELPER_3(vfp_toshh, i32, f16, i32, fpst) -DEF_HELPER_3(vfp_toulh, i32, f16, i32, fpst) -DEF_HELPER_3(vfp_toslh, i32, f16, i32, fpst) -DEF_HELPER_3(vfp_touqh, i64, f16, i32, fpst) -DEF_HELPER_3(vfp_tosqh, i64, f16, i32, fpst) -DEF_HELPER_3(vfp_toshs, i32, f32, i32, fpst) -DEF_HELPER_3(vfp_tosls, i32, f32, i32, fpst) -DEF_HELPER_3(vfp_tosqs, i64, f32, i32, fpst) -DEF_HELPER_3(vfp_touhs, i32, f32, i32, fpst) -DEF_HELPER_3(vfp_touls, i32, f32, i32, fpst) -DEF_HELPER_3(vfp_touqs, i64, f32, i32, fpst) -DEF_HELPER_3(vfp_toshd, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_tosld, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_tosqd, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_touhd, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_tould, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_touqd, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_shtos, f32, i32, i32, fpst) -DEF_HELPER_3(vfp_sltos, f32, i32, i32, fpst) -DEF_HELPER_3(vfp_sqtos, f32, i64, i32, fpst) -DEF_HELPER_3(vfp_uhtos, f32, i32, i32, fpst) -DEF_HELPER_3(vfp_ultos, f32, i32, i32, fpst) -DEF_HELPER_3(vfp_uqtos, f32, i64, i32, fpst) -DEF_HELPER_3(vfp_shtod, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_sltod, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_sqtod, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_uhtod, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_ultod, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_uqtod, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_shtoh, f16, i32, i32, fpst) -DEF_HELPER_3(vfp_uhtoh, f16, i32, i32, fpst) -DEF_HELPER_3(vfp_sltoh, f16, i32, i32, fpst) -DEF_HELPER_3(vfp_ultoh, f16, i32, i32, fpst) -DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, fpst) -DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, fpst) - -DEF_HELPER_3(vfp_shtos_round_to_nearest, f32, i32, i32, fpst) -DEF_HELPER_3(vfp_sltos_round_to_nearest, f32, i32, i32, fpst) -DEF_HELPER_3(vfp_uhtos_round_to_nearest, f32, i32, i32, fpst) -DEF_HELPER_3(vfp_ultos_round_to_nearest, f32, i32, i32, fpst) -DEF_HELPER_3(vfp_shtod_round_to_nearest, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_sltod_round_to_nearest, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_uhtod_round_to_nearest, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_ultod_round_to_nearest, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_shtoh_round_to_nearest, f16, i32, i32, fpst) -DEF_HELPER_3(vfp_uhtoh_round_to_nearest, f16, i32, i32, fpst) -DEF_HELPER_3(vfp_sltoh_round_to_nearest, f16, i32, i32, fpst) -DEF_HELPER_3(vfp_ultoh_round_to_nearest, f16, i32, i32, fpst) - -DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, fpst) - -DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f32, TCG_CALL_NO_RWG, f32, f16, fpst, i32) -DEF_HELPER_FLAGS_3(vfp_fcvt_f32_to_f16, TCG_CALL_NO_RWG, f16, f32, fpst, i32) -DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f64, TCG_CALL_NO_RWG, f64, f16, fpst, i32) -DEF_HELPER_FLAGS_3(vfp_fcvt_f64_to_f16, TCG_CALL_NO_RWG, f16, f64, fpst, i32) - -DEF_HELPER_4(vfp_muladdd, f64, f64, f64, f64, fpst) -DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, fpst) -DEF_HELPER_4(vfp_muladdh, f16, f16, f16, f16, fpst) - -DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, fpst) -DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, fpst) -DEF_HELPER_FLAGS_2(recpe_rpres_f32, TCG_CALL_NO_RWG, f32, f32, fpst) -DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, fpst) -DEF_HELPER_FLAGS_2(rsqrte_f16, TCG_CALL_NO_RWG, f16, f16, fpst) -DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, fpst) -DEF_HELPER_FLAGS_2(rsqrte_rpres_f32, TCG_CALL_NO_RWG, f32, f32, fpst) -DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, fpst) -DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32) -DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32) -DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64) - -DEF_HELPER_3(shl_cc, i32, env, i32, i32) -DEF_HELPER_3(shr_cc, i32, env, i32, i32) -DEF_HELPER_3(sar_cc, i32, env, i32, i32) -DEF_HELPER_3(ror_cc, i32, env, i32, i32) - -DEF_HELPER_FLAGS_2(rinth_exact, TCG_CALL_NO_RWG, f16, f16, fpst) -DEF_HELPER_FLAGS_2(rints_exact, TCG_CALL_NO_RWG, f32, f32, fpst) -DEF_HELPER_FLAGS_2(rintd_exact, TCG_CALL_NO_RWG, f64, f64, fpst) -DEF_HELPER_FLAGS_2(rinth, TCG_CALL_NO_RWG, f16, f16, fpst) -DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG, f32, f32, fpst) -DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, fpst) - -DEF_HELPER_FLAGS_2(vjcvt, TCG_CALL_NO_RWG, i32, f64, env) -DEF_HELPER_FLAGS_2(fjcvtzs, TCG_CALL_NO_RWG, i64, f64, fpst) - -DEF_HELPER_FLAGS_3(check_hcr_el2_trap, TCG_CALL_NO_WG, void, env, i32, i32) - -/* neon_helper.c */ -DEF_HELPER_2(neon_pmin_u8, i32, i32, i32) -DEF_HELPER_2(neon_pmin_s8, i32, i32, i32) -DEF_HELPER_2(neon_pmin_u16, i32, i32, i32) -DEF_HELPER_2(neon_pmin_s16, i32, i32, i32) -DEF_HELPER_2(neon_pmax_u8, i32, i32, i32) -DEF_HELPER_2(neon_pmax_s8, i32, i32, i32) -DEF_HELPER_2(neon_pmax_u16, i32, i32, i32) -DEF_HELPER_2(neon_pmax_s16, i32, i32, i32) - -DEF_HELPER_2(neon_shl_u16, i32, i32, i32) -DEF_HELPER_2(neon_shl_s16, i32, i32, i32) -DEF_HELPER_2(neon_rshl_u8, i32, i32, i32) -DEF_HELPER_2(neon_rshl_s8, i32, i32, i32) -DEF_HELPER_2(neon_rshl_u16, i32, i32, i32) -DEF_HELPER_2(neon_rshl_s16, i32, i32, i32) -DEF_HELPER_2(neon_rshl_u32, i32, i32, i32) -DEF_HELPER_2(neon_rshl_s32, i32, i32, i32) -DEF_HELPER_2(neon_rshl_u64, i64, i64, i64) -DEF_HELPER_2(neon_rshl_s64, i64, i64, i64) -DEF_HELPER_3(neon_qshl_u8, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_s8, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_u16, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_s16, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_u32, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_s32, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_u64, i64, env, i64, i64) -DEF_HELPER_3(neon_qshl_s64, i64, env, i64, i64) -DEF_HELPER_3(neon_qshlu_s8, i32, env, i32, i32) -DEF_HELPER_3(neon_qshlu_s16, i32, env, i32, i32) -DEF_HELPER_3(neon_qshlu_s32, i32, env, i32, i32) -DEF_HELPER_3(neon_qshlu_s64, i64, env, i64, i64) -DEF_HELPER_3(neon_qrshl_u8, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_s8, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_u16, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_s16, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_u32, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_s32, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_u64, i64, env, i64, i64) -DEF_HELPER_3(neon_qrshl_s64, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(neon_sqshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_sqshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_sqshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_sqshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_uqshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_uqshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_uqshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_uqshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_sqrshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_sqrshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_sqrshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_sqrshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_uqrshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_uqrshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_uqrshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_uqrshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_4(neon_sqshli_b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_4(neon_sqshli_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_4(neon_sqshli_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_4(neon_sqshli_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_4(neon_uqshli_b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_4(neon_uqshli_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_4(neon_uqshli_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_4(neon_uqshli_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_4(neon_sqshlui_b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_4(neon_sqshlui_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_4(neon_sqshlui_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_4(neon_sqshlui_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) - -DEF_HELPER_FLAGS_4(gvec_srshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_srshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_srshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_srshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_urshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_urshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_urshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_urshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_2(neon_add_u8, i32, i32, i32) -DEF_HELPER_2(neon_add_u16, i32, i32, i32) -DEF_HELPER_2(neon_sub_u8, i32, i32, i32) -DEF_HELPER_2(neon_sub_u16, i32, i32, i32) -DEF_HELPER_2(neon_mul_u8, i32, i32, i32) -DEF_HELPER_2(neon_mul_u16, i32, i32, i32) - -DEF_HELPER_2(neon_tst_u8, i32, i32, i32) -DEF_HELPER_2(neon_tst_u16, i32, i32, i32) -DEF_HELPER_2(neon_tst_u32, i32, i32, i32) - -DEF_HELPER_1(neon_clz_u8, i32, i32) -DEF_HELPER_1(neon_clz_u16, i32, i32) -DEF_HELPER_1(neon_cls_s8, i32, i32) -DEF_HELPER_1(neon_cls_s16, i32, i32) -DEF_HELPER_1(neon_cls_s32, i32, i32) -DEF_HELPER_FLAGS_3(gvec_cnt_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_rbit_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_3(neon_qdmulh_s16, i32, env, i32, i32) -DEF_HELPER_3(neon_qrdmulh_s16, i32, env, i32, i32) -DEF_HELPER_4(neon_qrdmlah_s16, i32, env, i32, i32, i32) -DEF_HELPER_4(neon_qrdmlsh_s16, i32, env, i32, i32, i32) -DEF_HELPER_3(neon_qdmulh_s32, i32, env, i32, i32) -DEF_HELPER_3(neon_qrdmulh_s32, i32, env, i32, i32) -DEF_HELPER_4(neon_qrdmlah_s32, i32, env, s32, s32, s32) -DEF_HELPER_4(neon_qrdmlsh_s32, i32, env, s32, s32, s32) - -DEF_HELPER_1(neon_narrow_u8, i64, i64) -DEF_HELPER_1(neon_narrow_u16, i64, i64) -DEF_HELPER_2(neon_unarrow_sat8, i64, env, i64) -DEF_HELPER_2(neon_narrow_sat_u8, i64, env, i64) -DEF_HELPER_2(neon_narrow_sat_s8, i64, env, i64) -DEF_HELPER_2(neon_unarrow_sat16, i64, env, i64) -DEF_HELPER_2(neon_narrow_sat_u16, i64, env, i64) -DEF_HELPER_2(neon_narrow_sat_s16, i64, env, i64) -DEF_HELPER_2(neon_unarrow_sat32, i64, env, i64) -DEF_HELPER_2(neon_narrow_sat_u32, i64, env, i64) -DEF_HELPER_2(neon_narrow_sat_s32, i64, env, i64) -DEF_HELPER_1(neon_narrow_high_u8, i32, i64) -DEF_HELPER_1(neon_narrow_high_u16, i32, i64) -DEF_HELPER_1(neon_narrow_round_high_u8, i32, i64) -DEF_HELPER_1(neon_narrow_round_high_u16, i32, i64) -DEF_HELPER_1(neon_widen_u8, i64, i32) -DEF_HELPER_1(neon_widen_s8, i64, i32) -DEF_HELPER_1(neon_widen_u16, i64, i32) -DEF_HELPER_1(neon_widen_s16, i64, i32) - -DEF_HELPER_FLAGS_1(neon_addlp_s8, TCG_CALL_NO_RWG_SE, i64, i64) -DEF_HELPER_FLAGS_1(neon_addlp_s16, TCG_CALL_NO_RWG_SE, i64, i64) -DEF_HELPER_3(neon_addl_saturate_s32, i64, env, i64, i64) -DEF_HELPER_3(neon_addl_saturate_s64, i64, env, i64, i64) -DEF_HELPER_2(neon_abdl_u16, i64, i32, i32) -DEF_HELPER_2(neon_abdl_s16, i64, i32, i32) -DEF_HELPER_2(neon_abdl_u32, i64, i32, i32) -DEF_HELPER_2(neon_abdl_s32, i64, i32, i32) -DEF_HELPER_2(neon_abdl_u64, i64, i32, i32) -DEF_HELPER_2(neon_abdl_s64, i64, i32, i32) -DEF_HELPER_2(neon_mull_u8, i64, i32, i32) -DEF_HELPER_2(neon_mull_s8, i64, i32, i32) -DEF_HELPER_2(neon_mull_u16, i64, i32, i32) -DEF_HELPER_2(neon_mull_s16, i64, i32, i32) - -DEF_HELPER_1(neon_negl_u16, i64, i64) -DEF_HELPER_1(neon_negl_u32, i64, i64) - -DEF_HELPER_FLAGS_2(neon_qabs_s8, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qabs_s16, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qabs_s32, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qabs_s64, TCG_CALL_NO_RWG, i64, env, i64) -DEF_HELPER_FLAGS_2(neon_qneg_s8, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qneg_s16, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qneg_s32, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qneg_s64, TCG_CALL_NO_RWG, i64, env, i64) - -DEF_HELPER_3(neon_ceq_f32, i32, i32, i32, fpst) -DEF_HELPER_3(neon_cge_f32, i32, i32, i32, fpst) -DEF_HELPER_3(neon_cgt_f32, i32, i32, i32, fpst) -DEF_HELPER_3(neon_acge_f32, i32, i32, i32, fpst) -DEF_HELPER_3(neon_acgt_f32, i32, i32, i32, fpst) -DEF_HELPER_3(neon_acge_f64, i64, i64, i64, fpst) -DEF_HELPER_3(neon_acgt_f64, i64, i64, i64, fpst) - -/* iwmmxt_helper.c */ -DEF_HELPER_2(iwmmxt_maddsq, i64, i64, i64) -DEF_HELPER_2(iwmmxt_madduq, i64, i64, i64) -DEF_HELPER_2(iwmmxt_sadb, i64, i64, i64) -DEF_HELPER_2(iwmmxt_sadw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_mulslw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_mulshw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_mululw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_muluhw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_macsw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_macuw, i64, i64, i64) -DEF_HELPER_1(iwmmxt_setpsr_nz, i32, i64) - -#define DEF_IWMMXT_HELPER_SIZE_ENV(name) \ -DEF_HELPER_3(iwmmxt_##name##b, i64, env, i64, i64) \ -DEF_HELPER_3(iwmmxt_##name##w, i64, env, i64, i64) \ -DEF_HELPER_3(iwmmxt_##name##l, i64, env, i64, i64) \ - -DEF_IWMMXT_HELPER_SIZE_ENV(unpackl) -DEF_IWMMXT_HELPER_SIZE_ENV(unpackh) - -DEF_HELPER_2(iwmmxt_unpacklub, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackluw, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpacklul, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhub, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhuw, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhul, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpacklsb, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpacklsw, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpacklsl, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhsb, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhsw, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhsl, i64, env, i64) - -DEF_IWMMXT_HELPER_SIZE_ENV(cmpeq) -DEF_IWMMXT_HELPER_SIZE_ENV(cmpgtu) -DEF_IWMMXT_HELPER_SIZE_ENV(cmpgts) - -DEF_IWMMXT_HELPER_SIZE_ENV(mins) -DEF_IWMMXT_HELPER_SIZE_ENV(minu) -DEF_IWMMXT_HELPER_SIZE_ENV(maxs) -DEF_IWMMXT_HELPER_SIZE_ENV(maxu) - -DEF_IWMMXT_HELPER_SIZE_ENV(subn) -DEF_IWMMXT_HELPER_SIZE_ENV(addn) -DEF_IWMMXT_HELPER_SIZE_ENV(subu) -DEF_IWMMXT_HELPER_SIZE_ENV(addu) -DEF_IWMMXT_HELPER_SIZE_ENV(subs) -DEF_IWMMXT_HELPER_SIZE_ENV(adds) - -DEF_HELPER_3(iwmmxt_avgb0, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_avgb1, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_avgw0, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_avgw1, i64, env, i64, i64) - -DEF_HELPER_3(iwmmxt_align, i64, i64, i64, i32) -DEF_HELPER_4(iwmmxt_insr, i64, i64, i32, i32, i32) - -DEF_HELPER_1(iwmmxt_bcstb, i64, i32) -DEF_HELPER_1(iwmmxt_bcstw, i64, i32) -DEF_HELPER_1(iwmmxt_bcstl, i64, i32) - -DEF_HELPER_1(iwmmxt_addcb, i64, i64) -DEF_HELPER_1(iwmmxt_addcw, i64, i64) -DEF_HELPER_1(iwmmxt_addcl, i64, i64) - -DEF_HELPER_1(iwmmxt_msbb, i32, i64) -DEF_HELPER_1(iwmmxt_msbw, i32, i64) -DEF_HELPER_1(iwmmxt_msbl, i32, i64) - -DEF_HELPER_3(iwmmxt_srlw, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_srll, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_srlq, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sllw, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_slll, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sllq, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sraw, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sral, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sraq, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_rorw, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_rorl, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_rorq, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_shufh, i64, env, i64, i32) - -DEF_HELPER_3(iwmmxt_packuw, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packul, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packuq, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packsw, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packsl, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packsq, i64, env, i64, i64) - -DEF_HELPER_3(iwmmxt_muladdsl, i64, i64, i32, i32) -DEF_HELPER_3(iwmmxt_muladdsw, i64, i64, i32, i32) -DEF_HELPER_3(iwmmxt_muladdswl, i64, i64, i32, i32) - -DEF_HELPER_FLAGS_2(neon_unzip8, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_unzip16, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qunzip8, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qunzip16, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qunzip32, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_zip8, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_zip16, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qzip8, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qzip16, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qzip32, TCG_CALL_NO_RWG, void, ptr, ptr) - -DEF_HELPER_FLAGS_4(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_aesd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(crypto_aesimc, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(crypto_sha1su0, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sha1c, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sha1p, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sha1m, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(crypto_sha1h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(crypto_sha1su1, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(crypto_sha256h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sha256h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(crypto_sha256su0, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sha256su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(crypto_sha512h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sha512h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(crypto_sha512su0, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sha512su1, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(crypto_sm3tt1a, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sm3tt1b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sm3tt2a, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sm3tt2b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sm3partw1, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sm3partw2, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(crypto_rax1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) -DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) - -DEF_HELPER_FLAGS_5(gvec_qrdmlah_s16, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s16, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_qrdmlah_s32, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s32, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(sve2_sqrdmlah_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlah_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlah_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlah_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(gvec_sdot_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_udot_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sdot_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_udot_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_usdot_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(gvec_sdot_idx_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_udot_idx_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sdot_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_udot_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sudot_idx_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_usdot_idx_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(gvec_fcaddh, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_6(gvec_fcmlah, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_fcmlah_idx, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_fcmlas, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_fcmlas_idx, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_fcmlad, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_sstoh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_sitos, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_ustoh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_uitos, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_tosszh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_tosizs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_touszh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_touizs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_vcvt_sf, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_uf, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fu, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_vcvt_sh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_uh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hu, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_vcvt_sd, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_ud, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rz_ds, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rz_du, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sd, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ud, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ss, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rm_us, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rm_uh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_vrint_rm_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vrint_rm_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_vrintx_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vrintx_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_frecpe_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_frecpe_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_frecpe_rpres_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_frecpe_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_frsqrte_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_frsqrte_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_frsqrte_rpres_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_frsqrte_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_fcgt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_fcgt0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_fcgt0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_fcge0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_fcge0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_fcge0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_fceq0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_fceq0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_fceq0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_fcle0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_fcle0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_fcle0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_fclt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_fclt0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_fclt0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fadd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fadd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fsub_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fsub_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fsub_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fmul_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmul_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmul_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_ah_fabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_ah_fabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_ah_fabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fceq_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fceq_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fceq_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fcge_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fcge_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fcge_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fcgt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fcgt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fcgt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_facge_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_facge_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_facge_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_facgt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_facgt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_facgt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fmax_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmax_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmax_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fmin_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmin_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmin_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fmaxnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmaxnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmaxnum_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fminnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fminnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fminnum_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_recps_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_recps_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_rsqrts_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_rsqrts_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fmla_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fmls_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmls_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_vfma_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_vfma_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_vfma_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_vfms_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_vfms_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_vfms_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_ah_vfms_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_ah_vfms_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_ah_vfms_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_ftsmul_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_ftsmul_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_ftsmul_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fmul_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmul_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmul_idx_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fmla_nf_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmla_nf_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fmls_nf_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmls_nf_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_6(gvec_fmla_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_fmla_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_fmla_idx_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_6(gvec_fmls_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_fmls_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_fmls_idx_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_6(gvec_ah_fmls_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_ah_fmls_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_ah_fmls_idx_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_uqadd_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uqadd_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uqadd_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uqadd_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sqadd_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sqadd_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sqadd_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sqadd_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uqsub_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uqsub_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uqsub_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uqsub_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sqsub_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sqsub_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sqsub_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sqsub_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_usqadd_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_usqadd_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_usqadd_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_usqadd_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_suqadd_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_suqadd_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_suqadd_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_suqadd_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(gvec_fmlal_a32, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(gvec_fmlal_a64, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a32, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a64, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, env, i32) - -DEF_HELPER_FLAGS_2(frint32_s, TCG_CALL_NO_RWG, f32, f32, fpst) -DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f32, fpst) -DEF_HELPER_FLAGS_2(frint32_d, TCG_CALL_NO_RWG, f64, f64, fpst) -DEF_HELPER_FLAGS_2(frint64_d, TCG_CALL_NO_RWG, f64, f64, fpst) - -DEF_HELPER_FLAGS_3(gvec_ceq0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_ceq0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_clt0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_clt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_cle0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_cle0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_cgt0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_cgt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_cge0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_cge0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_smulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_smulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_smulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_smulh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_umulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_umulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_umulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_umulh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_sshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_sshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_ushl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_ushl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_pmul_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_pmull_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(neon_pmull_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(gvec_ssra_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_ssra_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_ssra_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_ssra_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(gvec_usra_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_usra_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_usra_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_usra_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(gvec_srshr_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_srshr_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_srshr_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_srshr_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(gvec_urshr_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_urshr_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_urshr_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_urshr_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(gvec_srsra_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_srsra_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_srsra_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_srsra_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(gvec_ursra_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_ursra_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_ursra_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_ursra_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(gvec_sri_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_sri_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_sri_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_sri_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(gvec_sli_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_sli_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_sli_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_sli_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_sabd_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_sabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_sabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_sabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_uabd_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_uabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_uabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_uabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_saba_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_saba_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_saba_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_saba_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_uaba_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_uaba_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_uaba_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_uaba_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_mul_idx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_mul_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_mul_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(gvec_mla_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_mla_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_mla_idx_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(gvec_mls_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_mls_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_mls_idx_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(neon_sqdmulh_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_sqdmulh_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(neon_sqrdmulh_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_sqrdmulh_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(neon_sqdmulh_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_sqdmulh_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(neon_sqrdmulh_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_sqrdmulh_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(neon_sqrdmlah_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_sqrdmlah_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(neon_sqrdmlsh_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_sqrdmlsh_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(sve2_sqdmulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqdmulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqdmulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqdmulh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(sve2_sqdmulh_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqdmulh_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqdmulh_idx_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_6(sve2_fmlal_zzzw_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_6(sve2_fmlal_zzxw_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, env, i32) - -DEF_HELPER_FLAGS_4(gvec_xar_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(gvec_smmla_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_ummla_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_usmmla_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_6(gvec_bfdot, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_6(gvec_bfdot_idx, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, env, i32) - -DEF_HELPER_FLAGS_6(gvec_bfmmla, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, env, i32) - -DEF_HELPER_FLAGS_6(gvec_bfmlal, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_sclamp_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sclamp_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sclamp_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sclamp_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(gvec_uclamp_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uclamp_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uclamp_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(gvec_faddp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_faddp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_faddp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fmaxp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmaxp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmaxp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fminp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fminp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fminp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fmaxnump_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmaxnump_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmaxnump_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fminnump_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fminnump_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fminnump_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_addp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_addp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_addp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_addp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_smaxp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_smaxp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_smaxp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_sminp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_sminp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_sminp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_umaxp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_umaxp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_umaxp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_uminp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_uminp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_uminp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(gvec_urecpe_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_ursqrte_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +#include "tcg/helper.h" #ifdef TARGET_AARCH64 #include "tcg/helper-a64.h" diff --git a/target/arm/tcg/helper.h b/target/arm/tcg/helper.h new file mode 100644 index 00000000000..80db7c2c37a --- /dev/null +++ b/target/arm/tcg/helper.h @@ -0,0 +1,1153 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +DEF_HELPER_FLAGS_1(sxtb16, TCG_CALL_NO_RWG_SE, i32, i32) +DEF_HELPER_FLAGS_1(uxtb16, TCG_CALL_NO_RWG_SE, i32, i32) + +DEF_HELPER_3(add_setq, i32, env, i32, i32) +DEF_HELPER_3(add_saturate, i32, env, i32, i32) +DEF_HELPER_3(sub_saturate, i32, env, i32, i32) +DEF_HELPER_3(add_usaturate, i32, env, i32, i32) +DEF_HELPER_3(sub_usaturate, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(sdiv, TCG_CALL_NO_RWG, s32, env, s32, s32) +DEF_HELPER_FLAGS_3(udiv, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_1(rbit, TCG_CALL_NO_RWG_SE, i32, i32) + +#define PAS_OP(pfx) \ + DEF_HELPER_3(pfx ## add8, i32, i32, i32, ptr) \ + DEF_HELPER_3(pfx ## sub8, i32, i32, i32, ptr) \ + DEF_HELPER_3(pfx ## sub16, i32, i32, i32, ptr) \ + DEF_HELPER_3(pfx ## add16, i32, i32, i32, ptr) \ + DEF_HELPER_3(pfx ## addsubx, i32, i32, i32, ptr) \ + DEF_HELPER_3(pfx ## subaddx, i32, i32, i32, ptr) + +PAS_OP(s) +PAS_OP(u) +#undef PAS_OP + +#define PAS_OP(pfx) \ + DEF_HELPER_2(pfx ## add8, i32, i32, i32) \ + DEF_HELPER_2(pfx ## sub8, i32, i32, i32) \ + DEF_HELPER_2(pfx ## sub16, i32, i32, i32) \ + DEF_HELPER_2(pfx ## add16, i32, i32, i32) \ + DEF_HELPER_2(pfx ## addsubx, i32, i32, i32) \ + DEF_HELPER_2(pfx ## subaddx, i32, i32, i32) +PAS_OP(q) +PAS_OP(sh) +PAS_OP(uq) +PAS_OP(uh) +#undef PAS_OP + +DEF_HELPER_3(ssat, i32, env, i32, i32) +DEF_HELPER_3(usat, i32, env, i32, i32) +DEF_HELPER_3(ssat16, i32, env, i32, i32) +DEF_HELPER_3(usat16, i32, env, i32, i32) + +DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32) + +DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, + i32, i32, i32, i32) +DEF_HELPER_2(exception_internal, noreturn, env, i32) +DEF_HELPER_3(exception_with_syndrome, noreturn, env, i32, i32) +DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32) +DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) +DEF_HELPER_2(exception_swstep, noreturn, env, i32) +DEF_HELPER_2(exception_pc_alignment, noreturn, env, vaddr) +DEF_HELPER_1(setend, void, env) +DEF_HELPER_2(wfi, void, env, i32) +DEF_HELPER_1(wfe, void, env) +DEF_HELPER_2(wfit, void, env, i64) +DEF_HELPER_1(yield, void, env) +DEF_HELPER_1(pre_hvc, void, env) +DEF_HELPER_2(pre_smc, void, env, i32) +DEF_HELPER_1(vesb, void, env) + +DEF_HELPER_3(cpsr_write, void, env, i32, i32) +DEF_HELPER_2(cpsr_write_eret, void, env, i32) +DEF_HELPER_1(cpsr_read, i32, env) + +DEF_HELPER_3(v7m_msr, void, env, i32, i32) +DEF_HELPER_2(v7m_mrs, i32, env, i32) + +DEF_HELPER_2(v7m_bxns, void, env, i32) +DEF_HELPER_2(v7m_blxns, void, env, i32) + +DEF_HELPER_3(v7m_tt, i32, env, i32, i32) + +DEF_HELPER_1(v7m_preserve_fp_state, void, env) + +DEF_HELPER_2(v7m_vlstm, void, env, i32) +DEF_HELPER_2(v7m_vlldm, void, env, i32) + +DEF_HELPER_2(v8m_stackcheck, void, env, i32) + +DEF_HELPER_FLAGS_2(check_bxj_trap, TCG_CALL_NO_WG, void, env, i32) + +DEF_HELPER_4(access_check_cp_reg, cptr, env, i32, i32, i32) +DEF_HELPER_FLAGS_2(lookup_cp_reg, TCG_CALL_NO_RWG_SE, cptr, env, i32) +DEF_HELPER_FLAGS_2(tidcp_el0, TCG_CALL_NO_WG, void, env, i32) +DEF_HELPER_FLAGS_2(tidcp_el1, TCG_CALL_NO_WG, void, env, i32) +DEF_HELPER_3(set_cp_reg, void, env, cptr, i32) +DEF_HELPER_2(get_cp_reg, i32, env, cptr) +DEF_HELPER_3(set_cp_reg64, void, env, cptr, i64) +DEF_HELPER_2(get_cp_reg64, i64, env, cptr) + +DEF_HELPER_2(get_r13_banked, i32, env, i32) +DEF_HELPER_3(set_r13_banked, void, env, i32, i32) + +DEF_HELPER_3(mrs_banked, i32, env, i32, i32) +DEF_HELPER_4(msr_banked, void, env, i32, i32, i32) + +DEF_HELPER_2(get_user_reg, i32, env, i32) +DEF_HELPER_3(set_user_reg, void, env, i32, i32) + +DEF_HELPER_FLAGS_1(rebuild_hflags_m32_newel, TCG_CALL_NO_RWG, void, env) +DEF_HELPER_FLAGS_2(rebuild_hflags_m32, TCG_CALL_NO_RWG, void, env, int) +DEF_HELPER_FLAGS_1(rebuild_hflags_a32_newel, TCG_CALL_NO_RWG, void, env) +DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int) +DEF_HELPER_FLAGS_2(rebuild_hflags_a64, TCG_CALL_NO_RWG, void, env, int) + +DEF_HELPER_FLAGS_5(probe_access, TCG_CALL_NO_WG, void, env, vaddr, i32, i32, i32) + +DEF_HELPER_1(vfp_get_fpscr, i32, env) +DEF_HELPER_2(vfp_set_fpscr, void, env, i32) + +DEF_HELPER_3(vfp_addh, f16, f16, f16, fpst) +DEF_HELPER_3(vfp_adds, f32, f32, f32, fpst) +DEF_HELPER_3(vfp_addd, f64, f64, f64, fpst) +DEF_HELPER_3(vfp_subh, f16, f16, f16, fpst) +DEF_HELPER_3(vfp_subs, f32, f32, f32, fpst) +DEF_HELPER_3(vfp_subd, f64, f64, f64, fpst) +DEF_HELPER_3(vfp_mulh, f16, f16, f16, fpst) +DEF_HELPER_3(vfp_muls, f32, f32, f32, fpst) +DEF_HELPER_3(vfp_muld, f64, f64, f64, fpst) +DEF_HELPER_3(vfp_divh, f16, f16, f16, fpst) +DEF_HELPER_3(vfp_divs, f32, f32, f32, fpst) +DEF_HELPER_3(vfp_divd, f64, f64, f64, fpst) +DEF_HELPER_3(vfp_maxh, f16, f16, f16, fpst) +DEF_HELPER_3(vfp_maxs, f32, f32, f32, fpst) +DEF_HELPER_3(vfp_maxd, f64, f64, f64, fpst) +DEF_HELPER_3(vfp_minh, f16, f16, f16, fpst) +DEF_HELPER_3(vfp_mins, f32, f32, f32, fpst) +DEF_HELPER_3(vfp_mind, f64, f64, f64, fpst) +DEF_HELPER_3(vfp_maxnumh, f16, f16, f16, fpst) +DEF_HELPER_3(vfp_maxnums, f32, f32, f32, fpst) +DEF_HELPER_3(vfp_maxnumd, f64, f64, f64, fpst) +DEF_HELPER_3(vfp_minnumh, f16, f16, f16, fpst) +DEF_HELPER_3(vfp_minnums, f32, f32, f32, fpst) +DEF_HELPER_3(vfp_minnumd, f64, f64, f64, fpst) +DEF_HELPER_2(vfp_sqrth, f16, f16, fpst) +DEF_HELPER_2(vfp_sqrts, f32, f32, fpst) +DEF_HELPER_2(vfp_sqrtd, f64, f64, fpst) +DEF_HELPER_3(vfp_cmph, void, f16, f16, env) +DEF_HELPER_3(vfp_cmps, void, f32, f32, env) +DEF_HELPER_3(vfp_cmpd, void, f64, f64, env) +DEF_HELPER_3(vfp_cmpeh, void, f16, f16, env) +DEF_HELPER_3(vfp_cmpes, void, f32, f32, env) +DEF_HELPER_3(vfp_cmped, void, f64, f64, env) + +DEF_HELPER_2(vfp_fcvtds, f64, f32, fpst) +DEF_HELPER_2(vfp_fcvtsd, f32, f64, fpst) +DEF_HELPER_FLAGS_2(bfcvt, TCG_CALL_NO_RWG, i32, f32, fpst) +DEF_HELPER_FLAGS_2(bfcvt_pair, TCG_CALL_NO_RWG, i32, i64, fpst) + +DEF_HELPER_2(vfp_uitoh, f16, i32, fpst) +DEF_HELPER_2(vfp_uitos, f32, i32, fpst) +DEF_HELPER_2(vfp_uitod, f64, i32, fpst) +DEF_HELPER_2(vfp_sitoh, f16, i32, fpst) +DEF_HELPER_2(vfp_sitos, f32, i32, fpst) +DEF_HELPER_2(vfp_sitod, f64, i32, fpst) + +DEF_HELPER_2(vfp_touih, i32, f16, fpst) +DEF_HELPER_2(vfp_touis, i32, f32, fpst) +DEF_HELPER_2(vfp_touid, i32, f64, fpst) +DEF_HELPER_2(vfp_touizh, i32, f16, fpst) +DEF_HELPER_2(vfp_touizs, i32, f32, fpst) +DEF_HELPER_2(vfp_touizd, i32, f64, fpst) +DEF_HELPER_2(vfp_tosih, s32, f16, fpst) +DEF_HELPER_2(vfp_tosis, s32, f32, fpst) +DEF_HELPER_2(vfp_tosid, s32, f64, fpst) +DEF_HELPER_2(vfp_tosizh, s32, f16, fpst) +DEF_HELPER_2(vfp_tosizs, s32, f32, fpst) +DEF_HELPER_2(vfp_tosizd, s32, f64, fpst) + +DEF_HELPER_3(vfp_toshh_round_to_zero, i32, f16, i32, fpst) +DEF_HELPER_3(vfp_toslh_round_to_zero, i32, f16, i32, fpst) +DEF_HELPER_3(vfp_touhh_round_to_zero, i32, f16, i32, fpst) +DEF_HELPER_3(vfp_toulh_round_to_zero, i32, f16, i32, fpst) +DEF_HELPER_3(vfp_toshs_round_to_zero, i32, f32, i32, fpst) +DEF_HELPER_3(vfp_tosls_round_to_zero, i32, f32, i32, fpst) +DEF_HELPER_3(vfp_touhs_round_to_zero, i32, f32, i32, fpst) +DEF_HELPER_3(vfp_touls_round_to_zero, i32, f32, i32, fpst) +DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, fpst) +DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, fpst) +DEF_HELPER_3(vfp_tosqd_round_to_zero, i64, f64, i32, fpst) +DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, fpst) +DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, fpst) +DEF_HELPER_3(vfp_touqd_round_to_zero, i64, f64, i32, fpst) +DEF_HELPER_3(vfp_touhh, i32, f16, i32, fpst) +DEF_HELPER_3(vfp_toshh, i32, f16, i32, fpst) +DEF_HELPER_3(vfp_toulh, i32, f16, i32, fpst) +DEF_HELPER_3(vfp_toslh, i32, f16, i32, fpst) +DEF_HELPER_3(vfp_touqh, i64, f16, i32, fpst) +DEF_HELPER_3(vfp_tosqh, i64, f16, i32, fpst) +DEF_HELPER_3(vfp_toshs, i32, f32, i32, fpst) +DEF_HELPER_3(vfp_tosls, i32, f32, i32, fpst) +DEF_HELPER_3(vfp_tosqs, i64, f32, i32, fpst) +DEF_HELPER_3(vfp_touhs, i32, f32, i32, fpst) +DEF_HELPER_3(vfp_touls, i32, f32, i32, fpst) +DEF_HELPER_3(vfp_touqs, i64, f32, i32, fpst) +DEF_HELPER_3(vfp_toshd, i64, f64, i32, fpst) +DEF_HELPER_3(vfp_tosld, i64, f64, i32, fpst) +DEF_HELPER_3(vfp_tosqd, i64, f64, i32, fpst) +DEF_HELPER_3(vfp_touhd, i64, f64, i32, fpst) +DEF_HELPER_3(vfp_tould, i64, f64, i32, fpst) +DEF_HELPER_3(vfp_touqd, i64, f64, i32, fpst) +DEF_HELPER_3(vfp_shtos, f32, i32, i32, fpst) +DEF_HELPER_3(vfp_sltos, f32, i32, i32, fpst) +DEF_HELPER_3(vfp_sqtos, f32, i64, i32, fpst) +DEF_HELPER_3(vfp_uhtos, f32, i32, i32, fpst) +DEF_HELPER_3(vfp_ultos, f32, i32, i32, fpst) +DEF_HELPER_3(vfp_uqtos, f32, i64, i32, fpst) +DEF_HELPER_3(vfp_shtod, f64, i64, i32, fpst) +DEF_HELPER_3(vfp_sltod, f64, i64, i32, fpst) +DEF_HELPER_3(vfp_sqtod, f64, i64, i32, fpst) +DEF_HELPER_3(vfp_uhtod, f64, i64, i32, fpst) +DEF_HELPER_3(vfp_ultod, f64, i64, i32, fpst) +DEF_HELPER_3(vfp_uqtod, f64, i64, i32, fpst) +DEF_HELPER_3(vfp_shtoh, f16, i32, i32, fpst) +DEF_HELPER_3(vfp_uhtoh, f16, i32, i32, fpst) +DEF_HELPER_3(vfp_sltoh, f16, i32, i32, fpst) +DEF_HELPER_3(vfp_ultoh, f16, i32, i32, fpst) +DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, fpst) +DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, fpst) + +DEF_HELPER_3(vfp_shtos_round_to_nearest, f32, i32, i32, fpst) +DEF_HELPER_3(vfp_sltos_round_to_nearest, f32, i32, i32, fpst) +DEF_HELPER_3(vfp_uhtos_round_to_nearest, f32, i32, i32, fpst) +DEF_HELPER_3(vfp_ultos_round_to_nearest, f32, i32, i32, fpst) +DEF_HELPER_3(vfp_shtod_round_to_nearest, f64, i64, i32, fpst) +DEF_HELPER_3(vfp_sltod_round_to_nearest, f64, i64, i32, fpst) +DEF_HELPER_3(vfp_uhtod_round_to_nearest, f64, i64, i32, fpst) +DEF_HELPER_3(vfp_ultod_round_to_nearest, f64, i64, i32, fpst) +DEF_HELPER_3(vfp_shtoh_round_to_nearest, f16, i32, i32, fpst) +DEF_HELPER_3(vfp_uhtoh_round_to_nearest, f16, i32, i32, fpst) +DEF_HELPER_3(vfp_sltoh_round_to_nearest, f16, i32, i32, fpst) +DEF_HELPER_3(vfp_ultoh_round_to_nearest, f16, i32, i32, fpst) + +DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, fpst) + +DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f32, TCG_CALL_NO_RWG, f32, f16, fpst, i32) +DEF_HELPER_FLAGS_3(vfp_fcvt_f32_to_f16, TCG_CALL_NO_RWG, f16, f32, fpst, i32) +DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f64, TCG_CALL_NO_RWG, f64, f16, fpst, i32) +DEF_HELPER_FLAGS_3(vfp_fcvt_f64_to_f16, TCG_CALL_NO_RWG, f16, f64, fpst, i32) + +DEF_HELPER_4(vfp_muladdd, f64, f64, f64, f64, fpst) +DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, fpst) +DEF_HELPER_4(vfp_muladdh, f16, f16, f16, f16, fpst) + +DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, fpst) +DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, fpst) +DEF_HELPER_FLAGS_2(recpe_rpres_f32, TCG_CALL_NO_RWG, f32, f32, fpst) +DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, fpst) +DEF_HELPER_FLAGS_2(rsqrte_f16, TCG_CALL_NO_RWG, f16, f16, fpst) +DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, fpst) +DEF_HELPER_FLAGS_2(rsqrte_rpres_f32, TCG_CALL_NO_RWG, f32, f32, fpst) +DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, fpst) +DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32) +DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32) +DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64) + +DEF_HELPER_3(shl_cc, i32, env, i32, i32) +DEF_HELPER_3(shr_cc, i32, env, i32, i32) +DEF_HELPER_3(sar_cc, i32, env, i32, i32) +DEF_HELPER_3(ror_cc, i32, env, i32, i32) + +DEF_HELPER_FLAGS_2(rinth_exact, TCG_CALL_NO_RWG, f16, f16, fpst) +DEF_HELPER_FLAGS_2(rints_exact, TCG_CALL_NO_RWG, f32, f32, fpst) +DEF_HELPER_FLAGS_2(rintd_exact, TCG_CALL_NO_RWG, f64, f64, fpst) +DEF_HELPER_FLAGS_2(rinth, TCG_CALL_NO_RWG, f16, f16, fpst) +DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG, f32, f32, fpst) +DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, fpst) + +DEF_HELPER_FLAGS_2(vjcvt, TCG_CALL_NO_RWG, i32, f64, env) +DEF_HELPER_FLAGS_2(fjcvtzs, TCG_CALL_NO_RWG, i64, f64, fpst) + +DEF_HELPER_FLAGS_3(check_hcr_el2_trap, TCG_CALL_NO_WG, void, env, i32, i32) + +/* neon_helper.c */ +DEF_HELPER_2(neon_pmin_u8, i32, i32, i32) +DEF_HELPER_2(neon_pmin_s8, i32, i32, i32) +DEF_HELPER_2(neon_pmin_u16, i32, i32, i32) +DEF_HELPER_2(neon_pmin_s16, i32, i32, i32) +DEF_HELPER_2(neon_pmax_u8, i32, i32, i32) +DEF_HELPER_2(neon_pmax_s8, i32, i32, i32) +DEF_HELPER_2(neon_pmax_u16, i32, i32, i32) +DEF_HELPER_2(neon_pmax_s16, i32, i32, i32) + +DEF_HELPER_2(neon_shl_u16, i32, i32, i32) +DEF_HELPER_2(neon_shl_s16, i32, i32, i32) +DEF_HELPER_2(neon_rshl_u8, i32, i32, i32) +DEF_HELPER_2(neon_rshl_s8, i32, i32, i32) +DEF_HELPER_2(neon_rshl_u16, i32, i32, i32) +DEF_HELPER_2(neon_rshl_s16, i32, i32, i32) +DEF_HELPER_2(neon_rshl_u32, i32, i32, i32) +DEF_HELPER_2(neon_rshl_s32, i32, i32, i32) +DEF_HELPER_2(neon_rshl_u64, i64, i64, i64) +DEF_HELPER_2(neon_rshl_s64, i64, i64, i64) +DEF_HELPER_3(neon_qshl_u8, i32, env, i32, i32) +DEF_HELPER_3(neon_qshl_s8, i32, env, i32, i32) +DEF_HELPER_3(neon_qshl_u16, i32, env, i32, i32) +DEF_HELPER_3(neon_qshl_s16, i32, env, i32, i32) +DEF_HELPER_3(neon_qshl_u32, i32, env, i32, i32) +DEF_HELPER_3(neon_qshl_s32, i32, env, i32, i32) +DEF_HELPER_3(neon_qshl_u64, i64, env, i64, i64) +DEF_HELPER_3(neon_qshl_s64, i64, env, i64, i64) +DEF_HELPER_3(neon_qshlu_s8, i32, env, i32, i32) +DEF_HELPER_3(neon_qshlu_s16, i32, env, i32, i32) +DEF_HELPER_3(neon_qshlu_s32, i32, env, i32, i32) +DEF_HELPER_3(neon_qshlu_s64, i64, env, i64, i64) +DEF_HELPER_3(neon_qrshl_u8, i32, env, i32, i32) +DEF_HELPER_3(neon_qrshl_s8, i32, env, i32, i32) +DEF_HELPER_3(neon_qrshl_u16, i32, env, i32, i32) +DEF_HELPER_3(neon_qrshl_s16, i32, env, i32, i32) +DEF_HELPER_3(neon_qrshl_u32, i32, env, i32, i32) +DEF_HELPER_3(neon_qrshl_s32, i32, env, i32, i32) +DEF_HELPER_3(neon_qrshl_u64, i64, env, i64, i64) +DEF_HELPER_3(neon_qrshl_s64, i64, env, i64, i64) +DEF_HELPER_FLAGS_5(neon_sqshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_sqshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_sqshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_sqshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_uqshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_uqshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_uqshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_uqshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_sqrshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_sqrshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_sqrshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_sqrshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_uqrshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_uqrshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_uqrshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_uqrshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_4(neon_sqshli_b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_4(neon_sqshli_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_4(neon_sqshli_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_4(neon_sqshli_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_4(neon_uqshli_b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_4(neon_uqshli_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_4(neon_uqshli_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_4(neon_uqshli_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_4(neon_sqshlui_b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_4(neon_sqshlui_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_4(neon_sqshlui_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_4(neon_sqshlui_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) + +DEF_HELPER_FLAGS_4(gvec_srshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_srshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_srshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_srshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_urshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_urshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_urshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_urshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_2(neon_add_u8, i32, i32, i32) +DEF_HELPER_2(neon_add_u16, i32, i32, i32) +DEF_HELPER_2(neon_sub_u8, i32, i32, i32) +DEF_HELPER_2(neon_sub_u16, i32, i32, i32) +DEF_HELPER_2(neon_mul_u8, i32, i32, i32) +DEF_HELPER_2(neon_mul_u16, i32, i32, i32) + +DEF_HELPER_2(neon_tst_u8, i32, i32, i32) +DEF_HELPER_2(neon_tst_u16, i32, i32, i32) +DEF_HELPER_2(neon_tst_u32, i32, i32, i32) + +DEF_HELPER_1(neon_clz_u8, i32, i32) +DEF_HELPER_1(neon_clz_u16, i32, i32) +DEF_HELPER_1(neon_cls_s8, i32, i32) +DEF_HELPER_1(neon_cls_s16, i32, i32) +DEF_HELPER_1(neon_cls_s32, i32, i32) +DEF_HELPER_FLAGS_3(gvec_cnt_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_rbit_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_3(neon_qdmulh_s16, i32, env, i32, i32) +DEF_HELPER_3(neon_qrdmulh_s16, i32, env, i32, i32) +DEF_HELPER_4(neon_qrdmlah_s16, i32, env, i32, i32, i32) +DEF_HELPER_4(neon_qrdmlsh_s16, i32, env, i32, i32, i32) +DEF_HELPER_3(neon_qdmulh_s32, i32, env, i32, i32) +DEF_HELPER_3(neon_qrdmulh_s32, i32, env, i32, i32) +DEF_HELPER_4(neon_qrdmlah_s32, i32, env, s32, s32, s32) +DEF_HELPER_4(neon_qrdmlsh_s32, i32, env, s32, s32, s32) + +DEF_HELPER_1(neon_narrow_u8, i64, i64) +DEF_HELPER_1(neon_narrow_u16, i64, i64) +DEF_HELPER_2(neon_unarrow_sat8, i64, env, i64) +DEF_HELPER_2(neon_narrow_sat_u8, i64, env, i64) +DEF_HELPER_2(neon_narrow_sat_s8, i64, env, i64) +DEF_HELPER_2(neon_unarrow_sat16, i64, env, i64) +DEF_HELPER_2(neon_narrow_sat_u16, i64, env, i64) +DEF_HELPER_2(neon_narrow_sat_s16, i64, env, i64) +DEF_HELPER_2(neon_unarrow_sat32, i64, env, i64) +DEF_HELPER_2(neon_narrow_sat_u32, i64, env, i64) +DEF_HELPER_2(neon_narrow_sat_s32, i64, env, i64) +DEF_HELPER_1(neon_narrow_high_u8, i32, i64) +DEF_HELPER_1(neon_narrow_high_u16, i32, i64) +DEF_HELPER_1(neon_narrow_round_high_u8, i32, i64) +DEF_HELPER_1(neon_narrow_round_high_u16, i32, i64) +DEF_HELPER_1(neon_widen_u8, i64, i32) +DEF_HELPER_1(neon_widen_s8, i64, i32) +DEF_HELPER_1(neon_widen_u16, i64, i32) +DEF_HELPER_1(neon_widen_s16, i64, i32) + +DEF_HELPER_FLAGS_1(neon_addlp_s8, TCG_CALL_NO_RWG_SE, i64, i64) +DEF_HELPER_FLAGS_1(neon_addlp_s16, TCG_CALL_NO_RWG_SE, i64, i64) +DEF_HELPER_3(neon_addl_saturate_s32, i64, env, i64, i64) +DEF_HELPER_3(neon_addl_saturate_s64, i64, env, i64, i64) +DEF_HELPER_2(neon_abdl_u16, i64, i32, i32) +DEF_HELPER_2(neon_abdl_s16, i64, i32, i32) +DEF_HELPER_2(neon_abdl_u32, i64, i32, i32) +DEF_HELPER_2(neon_abdl_s32, i64, i32, i32) +DEF_HELPER_2(neon_abdl_u64, i64, i32, i32) +DEF_HELPER_2(neon_abdl_s64, i64, i32, i32) +DEF_HELPER_2(neon_mull_u8, i64, i32, i32) +DEF_HELPER_2(neon_mull_s8, i64, i32, i32) +DEF_HELPER_2(neon_mull_u16, i64, i32, i32) +DEF_HELPER_2(neon_mull_s16, i64, i32, i32) + +DEF_HELPER_1(neon_negl_u16, i64, i64) +DEF_HELPER_1(neon_negl_u32, i64, i64) + +DEF_HELPER_FLAGS_2(neon_qabs_s8, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qabs_s16, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qabs_s32, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qabs_s64, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(neon_qneg_s8, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qneg_s16, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qneg_s32, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qneg_s64, TCG_CALL_NO_RWG, i64, env, i64) + +DEF_HELPER_3(neon_ceq_f32, i32, i32, i32, fpst) +DEF_HELPER_3(neon_cge_f32, i32, i32, i32, fpst) +DEF_HELPER_3(neon_cgt_f32, i32, i32, i32, fpst) +DEF_HELPER_3(neon_acge_f32, i32, i32, i32, fpst) +DEF_HELPER_3(neon_acgt_f32, i32, i32, i32, fpst) +DEF_HELPER_3(neon_acge_f64, i64, i64, i64, fpst) +DEF_HELPER_3(neon_acgt_f64, i64, i64, i64, fpst) + +/* iwmmxt_helper.c */ +DEF_HELPER_2(iwmmxt_maddsq, i64, i64, i64) +DEF_HELPER_2(iwmmxt_madduq, i64, i64, i64) +DEF_HELPER_2(iwmmxt_sadb, i64, i64, i64) +DEF_HELPER_2(iwmmxt_sadw, i64, i64, i64) +DEF_HELPER_2(iwmmxt_mulslw, i64, i64, i64) +DEF_HELPER_2(iwmmxt_mulshw, i64, i64, i64) +DEF_HELPER_2(iwmmxt_mululw, i64, i64, i64) +DEF_HELPER_2(iwmmxt_muluhw, i64, i64, i64) +DEF_HELPER_2(iwmmxt_macsw, i64, i64, i64) +DEF_HELPER_2(iwmmxt_macuw, i64, i64, i64) +DEF_HELPER_1(iwmmxt_setpsr_nz, i32, i64) + +#define DEF_IWMMXT_HELPER_SIZE_ENV(name) \ +DEF_HELPER_3(iwmmxt_##name##b, i64, env, i64, i64) \ +DEF_HELPER_3(iwmmxt_##name##w, i64, env, i64, i64) \ +DEF_HELPER_3(iwmmxt_##name##l, i64, env, i64, i64) \ + +DEF_IWMMXT_HELPER_SIZE_ENV(unpackl) +DEF_IWMMXT_HELPER_SIZE_ENV(unpackh) + +DEF_HELPER_2(iwmmxt_unpacklub, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpackluw, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpacklul, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpackhub, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpackhuw, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpackhul, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpacklsb, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpacklsw, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpacklsl, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpackhsb, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpackhsw, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpackhsl, i64, env, i64) + +DEF_IWMMXT_HELPER_SIZE_ENV(cmpeq) +DEF_IWMMXT_HELPER_SIZE_ENV(cmpgtu) +DEF_IWMMXT_HELPER_SIZE_ENV(cmpgts) + +DEF_IWMMXT_HELPER_SIZE_ENV(mins) +DEF_IWMMXT_HELPER_SIZE_ENV(minu) +DEF_IWMMXT_HELPER_SIZE_ENV(maxs) +DEF_IWMMXT_HELPER_SIZE_ENV(maxu) + +DEF_IWMMXT_HELPER_SIZE_ENV(subn) +DEF_IWMMXT_HELPER_SIZE_ENV(addn) +DEF_IWMMXT_HELPER_SIZE_ENV(subu) +DEF_IWMMXT_HELPER_SIZE_ENV(addu) +DEF_IWMMXT_HELPER_SIZE_ENV(subs) +DEF_IWMMXT_HELPER_SIZE_ENV(adds) + +DEF_HELPER_3(iwmmxt_avgb0, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_avgb1, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_avgw0, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_avgw1, i64, env, i64, i64) + +DEF_HELPER_3(iwmmxt_align, i64, i64, i64, i32) +DEF_HELPER_4(iwmmxt_insr, i64, i64, i32, i32, i32) + +DEF_HELPER_1(iwmmxt_bcstb, i64, i32) +DEF_HELPER_1(iwmmxt_bcstw, i64, i32) +DEF_HELPER_1(iwmmxt_bcstl, i64, i32) + +DEF_HELPER_1(iwmmxt_addcb, i64, i64) +DEF_HELPER_1(iwmmxt_addcw, i64, i64) +DEF_HELPER_1(iwmmxt_addcl, i64, i64) + +DEF_HELPER_1(iwmmxt_msbb, i32, i64) +DEF_HELPER_1(iwmmxt_msbw, i32, i64) +DEF_HELPER_1(iwmmxt_msbl, i32, i64) + +DEF_HELPER_3(iwmmxt_srlw, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_srll, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_srlq, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_sllw, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_slll, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_sllq, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_sraw, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_sral, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_sraq, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_rorw, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_rorl, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_rorq, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_shufh, i64, env, i64, i32) + +DEF_HELPER_3(iwmmxt_packuw, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_packul, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_packuq, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_packsw, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_packsl, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_packsq, i64, env, i64, i64) + +DEF_HELPER_3(iwmmxt_muladdsl, i64, i64, i32, i32) +DEF_HELPER_3(iwmmxt_muladdsw, i64, i64, i32, i32) +DEF_HELPER_3(iwmmxt_muladdswl, i64, i64, i32, i32) + +DEF_HELPER_FLAGS_2(neon_unzip8, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_unzip16, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qunzip8, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qunzip16, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qunzip32, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_zip8, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_zip16, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qzip8, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qzip16, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qzip32, TCG_CALL_NO_RWG, void, ptr, ptr) + +DEF_HELPER_FLAGS_4(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_aesd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(crypto_aesimc, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(crypto_sha1su0, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_sha1c, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_sha1p, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_sha1m, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(crypto_sha1h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(crypto_sha1su1, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(crypto_sha256h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_sha256h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(crypto_sha256su0, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_sha256su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(crypto_sha512h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_sha512h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(crypto_sha512su0, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_sha512su1, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(crypto_sm3tt1a, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_sm3tt1b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_sm3tt2a, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_sm3tt2b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_sm3partw1, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_sm3partw2, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(crypto_rax1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) +DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) + +DEF_HELPER_FLAGS_5(gvec_qrdmlah_s16, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s16, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_qrdmlah_s32, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s32, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve2_sqrdmlah_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_sqrdmlah_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_sqrdmlah_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_sqrdmlah_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(gvec_sdot_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_udot_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sdot_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_udot_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_usdot_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(gvec_sdot_idx_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_udot_idx_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sdot_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_udot_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sudot_idx_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_usdot_idx_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(gvec_fcaddh, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_6(gvec_fcmlah, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_6(gvec_fcmlah_idx, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_6(gvec_fcmlas, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_6(gvec_fcmlas_idx, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_6(gvec_fcmlad, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_sstoh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_sitos, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_ustoh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_uitos, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_tosszh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_tosizs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_touszh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_touizs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_vcvt_sf, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vcvt_uf, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fu, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_vcvt_sh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vcvt_uh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hu, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_vcvt_sd, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vcvt_ud, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vcvt_rz_ds, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vcvt_rz_du, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sd, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ud, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ss, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vcvt_rm_us, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vcvt_rm_uh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_vrint_rm_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vrint_rm_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_vrintx_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vrintx_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_frecpe_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_frecpe_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_frecpe_rpres_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_frecpe_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_frsqrte_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_frsqrte_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_frsqrte_rpres_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_frsqrte_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_fcgt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_fcgt0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_fcgt0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_fcge0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_fcge0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_fcge0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_fceq0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_fceq0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_fceq0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_fcle0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_fcle0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_fcle0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_fclt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_fclt0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_fclt0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fadd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fadd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fsub_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fsub_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fsub_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fmul_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmul_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmul_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_ah_fabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_ah_fabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_ah_fabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fceq_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fceq_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fceq_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fcge_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fcge_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fcge_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fcgt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fcgt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fcgt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_facge_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_facge_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_facge_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_facgt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_facgt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_facgt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fmax_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmax_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmax_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fmin_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmin_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmin_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fmaxnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmaxnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmaxnum_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fminnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fminnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fminnum_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_recps_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_recps_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_rsqrts_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_rsqrts_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fmla_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fmls_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmls_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_vfma_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_vfma_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_vfma_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_vfms_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_vfms_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_vfms_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_ah_vfms_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_ah_vfms_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_ah_vfms_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_ftsmul_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_ftsmul_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_ftsmul_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fmul_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmul_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmul_idx_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fmla_nf_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmla_nf_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fmls_nf_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmls_nf_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_6(gvec_fmla_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_6(gvec_fmla_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_6(gvec_fmla_idx_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_6(gvec_fmls_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_6(gvec_fmls_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_6(gvec_fmls_idx_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_6(gvec_ah_fmls_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_6(gvec_ah_fmls_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_6(gvec_ah_fmls_idx_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_uqadd_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uqadd_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uqadd_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uqadd_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sqadd_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sqadd_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sqadd_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sqadd_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uqsub_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uqsub_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uqsub_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uqsub_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sqsub_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sqsub_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sqsub_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sqsub_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_usqadd_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_usqadd_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_usqadd_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_usqadd_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_suqadd_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_suqadd_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_suqadd_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_suqadd_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(gvec_fmlal_a32, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_fmlal_a64, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a32, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a64, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_FLAGS_2(frint32_s, TCG_CALL_NO_RWG, f32, f32, fpst) +DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f32, fpst) +DEF_HELPER_FLAGS_2(frint32_d, TCG_CALL_NO_RWG, f64, f64, fpst) +DEF_HELPER_FLAGS_2(frint64_d, TCG_CALL_NO_RWG, f64, f64, fpst) + +DEF_HELPER_FLAGS_3(gvec_ceq0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_ceq0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_clt0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_clt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_cle0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_cle0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_cgt0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_cgt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_cge0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_cge0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_smulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_smulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_smulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_smulh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_umulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_umulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_umulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_umulh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_sshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_ushl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_ushl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_pmul_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_pmull_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(neon_pmull_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(gvec_ssra_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_ssra_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_ssra_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_ssra_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(gvec_usra_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_usra_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_usra_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_usra_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(gvec_srshr_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_srshr_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_srshr_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_srshr_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(gvec_urshr_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_urshr_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_urshr_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_urshr_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(gvec_srsra_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_srsra_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_srsra_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_srsra_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(gvec_ursra_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_ursra_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_ursra_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_ursra_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(gvec_sri_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_sri_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_sri_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_sri_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(gvec_sli_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_sli_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_sli_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_sli_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_sabd_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_uabd_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_uabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_uabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_uabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_saba_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_saba_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_saba_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_saba_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_uaba_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_uaba_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_uaba_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_uaba_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_mul_idx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_mul_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_mul_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(gvec_mla_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_mla_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_mla_idx_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(gvec_mls_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_mls_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_mls_idx_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(neon_sqdmulh_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(neon_sqdmulh_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(neon_sqrdmulh_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(neon_sqrdmulh_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(neon_sqdmulh_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(neon_sqdmulh_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(neon_sqrdmulh_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(neon_sqrdmulh_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(neon_sqrdmlah_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(neon_sqrdmlah_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(neon_sqrdmlsh_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(neon_sqrdmlsh_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve2_sqdmulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqdmulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqdmulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqdmulh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve2_sqrdmulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqrdmulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqrdmulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqrdmulh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve2_sqdmulh_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqdmulh_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqdmulh_idx_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_6(sve2_fmlal_zzzw_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_6(sve2_fmlal_zzxw_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, env, i32) + +DEF_HELPER_FLAGS_4(gvec_xar_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(gvec_smmla_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_ummla_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_usmmla_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_6(gvec_bfdot, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_6(gvec_bfdot_idx, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, env, i32) + +DEF_HELPER_FLAGS_6(gvec_bfmmla, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, env, i32) + +DEF_HELPER_FLAGS_6(gvec_bfmlal, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_sclamp_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sclamp_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sclamp_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sclamp_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(gvec_uclamp_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uclamp_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uclamp_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(gvec_faddp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_faddp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_faddp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fmaxp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmaxp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmaxp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fminp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fminp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fminp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fmaxnump_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmaxnump_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmaxnump_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fminnump_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fminnump_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fminnump_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_addp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_addp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_addp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_addp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_smaxp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_smaxp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_smaxp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_sminp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sminp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sminp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_umaxp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_umaxp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_umaxp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_uminp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_uminp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_uminp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(gvec_urecpe_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_ursqrte_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v8 16/48] target/arm/debug_helper: only include common helpers 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (14 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 15/48] target/arm/helper: extract common helpers Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 17/48] target/arm/debug_helper: remove target_ulong Pierrick Bouvier ` (31 subsequent siblings) 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Avoid pulling helper.h which contains TARGET_AARCH64. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/debug_helper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index de7999f6a94..cad0a5db707 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -11,10 +11,12 @@ #include "internals.h" #include "cpu-features.h" #include "cpregs.h" -#include "exec/helper-proto.h" #include "exec/watchpoint.h" #include "system/tcg.h" +#define HELPER_H "tcg/helper.h" +#include "exec/helper-proto.h.inc" + #ifdef CONFIG_TCG /* Return the Exception Level targeted by debug exceptions. */ static int arm_debug_target_el(CPUARMState *env) -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v8 17/48] target/arm/debug_helper: remove target_ulong 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (15 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 16/48] target/arm/debug_helper: only include " Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 18/48] target/arm/debug_helper: compile file twice (user, system) Pierrick Bouvier ` (30 subsequent siblings) 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/debug_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index cad0a5db707..69fb1d0d9ff 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -380,7 +380,7 @@ bool arm_debug_check_breakpoint(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; - target_ulong pc; + vaddr pc; int n; /* -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v8 18/48] target/arm/debug_helper: compile file twice (user, system) 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (16 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 17/48] target/arm/debug_helper: remove target_ulong Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 19/48] target/arm/helper: restrict include to common helpers Pierrick Bouvier ` (29 subsequent siblings) 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/meson.build | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index de214fe5d56..48a6bf59353 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -1,7 +1,6 @@ arm_ss = ss.source_set() arm_common_ss = ss.source_set() arm_ss.add(files( - 'debug_helper.c', 'gdbstub.c', 'helper.c', 'vfp_fpscr.c', @@ -29,11 +28,18 @@ arm_system_ss.add(files( arm_user_ss = ss.source_set() arm_user_ss.add(files('cpu.c')) arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files( - 'cpu32-stubs.c')) + 'cpu32-stubs.c', +)) +arm_user_ss.add(files( + 'debug_helper.c', +)) arm_common_system_ss.add(files('cpu.c'), capstone) arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files( 'cpu32-stubs.c')) +arm_common_system_ss.add(files( + 'debug_helper.c', +)) subdir('hvf') -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v8 19/48] target/arm/helper: restrict include to common helpers 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (17 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 18/48] target/arm/debug_helper: compile file twice (user, system) Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 20/48] target/arm/helper: replace target_ulong by vaddr Pierrick Bouvier ` (28 subsequent siblings) 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/helper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 4a2d1ecbfee..3795dccd16b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12,7 +12,6 @@ #include "cpu.h" #include "internals.h" #include "cpu-features.h" -#include "exec/helper-proto.h" #include "exec/page-protection.h" #include "exec/mmap-lock.h" #include "qemu/main-loop.h" @@ -35,6 +34,9 @@ #include "cpregs.h" #include "target/arm/gtimer.h" +#define HELPER_H "tcg/helper.h" +#include "exec/helper-proto.h.inc" + #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ static void switch_mode(CPUARMState *env, int mode); -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v8 20/48] target/arm/helper: replace target_ulong by vaddr 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (18 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 19/48] target/arm/helper: restrict include to common helpers Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 21/48] target/arm/helper: expose aarch64 cpu registration Pierrick Bouvier ` (27 subsequent siblings) 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3795dccd16b..d2607107eb9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10621,7 +10621,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; unsigned int new_el = env->exception.target_el; - target_ulong addr = env->cp15.vbar_el[new_el]; + vaddr addr = env->cp15.vbar_el[new_el]; unsigned int new_mode = aarch64_pstate_mode(new_el, true); unsigned int old_mode; unsigned int cur_el = arm_current_el(env); -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v8 21/48] target/arm/helper: expose aarch64 cpu registration 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (19 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 20/48] target/arm/helper: replace target_ulong by vaddr Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 22/48] target/arm/helper: remove remaining TARGET_AARCH64 Pierrick Bouvier ` (26 subsequent siblings) 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier associated define_arm_cp_regs are guarded by "cpu_isar_feature(aa64_*)", so it's safe to expose that code for arm target (32 bit). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/helper.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d2607107eb9..92a975bbf78 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6590,7 +6590,6 @@ static const ARMCPRegInfo zcr_reginfo[] = { .writefn = zcr_write, .raw_writefn = raw_write }, }; -#ifdef TARGET_AARCH64 static CPAccessResult access_tpidr2(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { @@ -6824,7 +6823,6 @@ static const ARMCPRegInfo nmi_reginfo[] = { .writefn = aa64_allint_write, .readfn = aa64_allint_read, .resetfn = arm_cp_reset_ignore }, }; -#endif /* TARGET_AARCH64 */ static void define_pmu_regs(ARMCPU *cpu) { @@ -7016,7 +7014,6 @@ static const ARMCPRegInfo lor_reginfo[] = { .type = ARM_CP_CONST, .resetvalue = 0 }, }; -#ifdef TARGET_AARCH64 static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { @@ -7509,8 +7506,6 @@ static const ARMCPRegInfo nv2_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.vncr_el2) }, }; -#endif /* TARGET_AARCH64 */ - static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { @@ -8951,7 +8946,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &hcrx_el2_reginfo); } -#ifdef TARGET_AARCH64 if (cpu_isar_feature(aa64_sme, cpu)) { define_arm_cp_regs(cpu, sme_reginfo); } @@ -9012,7 +9006,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_nmi, cpu)) { define_arm_cp_regs(cpu, nmi_reginfo); } -#endif if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v8 22/48] target/arm/helper: remove remaining TARGET_AARCH64 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (20 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 21/48] target/arm/helper: expose aarch64 cpu registration Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-13 10:06 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 23/48] target/arm/helper: compile file twice (user, system) Pierrick Bouvier ` (25 subsequent siblings) 47 siblings, 1 reply; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier They were hiding aarch64_sve_narrow_vq and aarch64_sve_change_el, which we can expose safely. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/helper.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 92a975bbf78..aae8554e8f2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -29,6 +29,7 @@ #include "qemu/guest-random.h" #ifdef CONFIG_TCG #include "accel/tcg/probe.h" +#include "accel/tcg/getpc.h" #include "semihosting/common-semi.h" #endif #include "cpregs.h" @@ -6565,9 +6566,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, */ new_len = sve_vqm1_for_el(env, cur_el); if (new_len < old_len) { -#ifdef TARGET_AARCH64 aarch64_sve_narrow_vq(env, new_len + 1); -#endif } } @@ -10625,9 +10624,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) * Note that new_el can never be 0. If cur_el is 0, then * el0_a64 is is_a64(), else el0_a64 is ignored. */ -#ifdef TARGET_AARCH64 aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); -#endif } if (cur_el < new_el) { @@ -11418,7 +11415,6 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env) return arm_mmu_idx_el(env, arm_current_el(env)); } -#ifdef TARGET_AARCH64 /* * The manual says that when SVE is enabled and VQ is widened the * implementation is allowed to zero the previously inaccessible @@ -11530,12 +11526,9 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el, /* When changing vector length, clear inaccessible state. */ if (new_len < old_len) { -#ifdef TARGET_AARCH64 aarch64_sve_narrow_vq(env, new_len + 1); -#endif } } -#endif #ifndef CONFIG_USER_ONLY ARMSecuritySpace arm_security_space(CPUARMState *env) -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v8 22/48] target/arm/helper: remove remaining TARGET_AARCH64 2025-05-12 18:04 ` [PATCH v8 22/48] target/arm/helper: remove remaining TARGET_AARCH64 Pierrick Bouvier @ 2025-05-13 10:06 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 71+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-13 10:06 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson On 12/5/25 20:04, Pierrick Bouvier wrote: > They were hiding aarch64_sve_narrow_vq and aarch64_sve_change_el, which > we can expose safely. > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/helper.c | 9 +-------- > 1 file changed, 1 insertion(+), 8 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v8 23/48] target/arm/helper: compile file twice (user, system) 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (21 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 22/48] target/arm/helper: remove remaining TARGET_AARCH64 Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-13 10:06 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 24/48] target/arm/vfp_fpscr: " Pierrick Bouvier ` (24 subsequent siblings) 47 siblings, 1 reply; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/meson.build | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 48a6bf59353..c8c80c3f969 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -2,7 +2,6 @@ arm_ss = ss.source_set() arm_common_ss = ss.source_set() arm_ss.add(files( 'gdbstub.c', - 'helper.c', 'vfp_fpscr.c', )) arm_ss.add(zlib) @@ -32,6 +31,7 @@ arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files( )) arm_user_ss.add(files( 'debug_helper.c', + 'helper.c', )) arm_common_system_ss.add(files('cpu.c'), capstone) @@ -39,6 +39,7 @@ arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files( 'cpu32-stubs.c')) arm_common_system_ss.add(files( 'debug_helper.c', + 'helper.c', )) subdir('hvf') -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v8 23/48] target/arm/helper: compile file twice (user, system) 2025-05-12 18:04 ` [PATCH v8 23/48] target/arm/helper: compile file twice (user, system) Pierrick Bouvier @ 2025-05-13 10:06 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 71+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-13 10:06 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson On 12/5/25 20:04, Pierrick Bouvier wrote: > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/meson.build | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) Nice! Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v8 24/48] target/arm/vfp_fpscr: compile file twice (user, system) 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (22 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 23/48] target/arm/helper: compile file twice (user, system) Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-13 10:07 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 25/48] target/arm/arch_dump: remove TARGET_AARCH64 conditionals Pierrick Bouvier ` (23 subsequent siblings) 47 siblings, 1 reply; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/meson.build | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index c8c80c3f969..06d479570e2 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -2,7 +2,6 @@ arm_ss = ss.source_set() arm_common_ss = ss.source_set() arm_ss.add(files( 'gdbstub.c', - 'vfp_fpscr.c', )) arm_ss.add(zlib) @@ -32,6 +31,7 @@ arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files( arm_user_ss.add(files( 'debug_helper.c', 'helper.c', + 'vfp_fpscr.c', )) arm_common_system_ss.add(files('cpu.c'), capstone) @@ -40,6 +40,7 @@ arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files( arm_common_system_ss.add(files( 'debug_helper.c', 'helper.c', + 'vfp_fpscr.c', )) subdir('hvf') -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v8 24/48] target/arm/vfp_fpscr: compile file twice (user, system) 2025-05-12 18:04 ` [PATCH v8 24/48] target/arm/vfp_fpscr: " Pierrick Bouvier @ 2025-05-13 10:07 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 71+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-13 10:07 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson On 12/5/25 20:04, Pierrick Bouvier wrote: > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/meson.build | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v8 25/48] target/arm/arch_dump: remove TARGET_AARCH64 conditionals 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (23 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 24/48] target/arm/vfp_fpscr: " Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 26/48] target/arm/arch_dump: compile file once (system) Pierrick Bouvier ` (22 subsequent siblings) 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Associated code is protected by cpu_isar_feature(aa64*) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/arch_dump.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index c40df4e7fd7..1dd79849c13 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -143,7 +143,6 @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f, return 0; } -#ifdef TARGET_AARCH64 static off_t sve_zreg_offset(uint32_t vq, int n) { off_t off = sizeof(struct aarch64_user_sve_header); @@ -231,7 +230,6 @@ static int aarch64_write_elf64_sve(WriteCoreDumpFunction f, return 0; } -#endif int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, DumpState *s) @@ -273,11 +271,9 @@ int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, return ret; } -#ifdef TARGET_AARCH64 if (cpu_isar_feature(aa64_sve, cpu)) { ret = aarch64_write_elf64_sve(f, env, cpuid, s); } -#endif return ret; } @@ -451,11 +447,9 @@ ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) if (class == ELFCLASS64) { note_size = AARCH64_PRSTATUS_NOTE_SIZE; note_size += AARCH64_PRFPREG_NOTE_SIZE; -#ifdef TARGET_AARCH64 if (cpu_isar_feature(aa64_sve, cpu)) { note_size += AARCH64_SVE_NOTE_SIZE(&cpu->env); } -#endif } else { note_size = ARM_PRSTATUS_NOTE_SIZE; if (cpu_isar_feature(aa32_vfp_simd, cpu)) { -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v8 26/48] target/arm/arch_dump: compile file once (system) 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (24 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 25/48] target/arm/arch_dump: remove TARGET_AARCH64 conditionals Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-13 10:07 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 27/48] target/arm/arm-powerctl: " Pierrick Bouvier ` (21 subsequent siblings) 47 siblings, 1 reply; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 06d479570e2..95a2b077dd6 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -15,7 +15,6 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( arm_system_ss = ss.source_set() arm_common_system_ss = ss.source_set() arm_system_ss.add(files( - 'arch_dump.c', 'arm-powerctl.c', 'arm-qmp-cmds.c', 'cortex-regs.c', @@ -38,6 +37,7 @@ arm_common_system_ss.add(files('cpu.c'), capstone) arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files( 'cpu32-stubs.c')) arm_common_system_ss.add(files( + 'arch_dump.c', 'debug_helper.c', 'helper.c', 'vfp_fpscr.c', -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v8 26/48] target/arm/arch_dump: compile file once (system) 2025-05-12 18:04 ` [PATCH v8 26/48] target/arm/arch_dump: compile file once (system) Pierrick Bouvier @ 2025-05-13 10:07 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 71+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-13 10:07 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson On 12/5/25 20:04, Pierrick Bouvier wrote: > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/meson.build | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v8 27/48] target/arm/arm-powerctl: compile file once (system) 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (25 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 26/48] target/arm/arch_dump: compile file once (system) Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-13 10:07 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 28/48] target/arm/cortex-regs: " Pierrick Bouvier ` (20 subsequent siblings) 47 siblings, 1 reply; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 95a2b077dd6..7db573f4a97 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -15,7 +15,6 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( arm_system_ss = ss.source_set() arm_common_system_ss = ss.source_set() arm_system_ss.add(files( - 'arm-powerctl.c', 'arm-qmp-cmds.c', 'cortex-regs.c', 'machine.c', @@ -38,6 +37,7 @@ arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files( 'cpu32-stubs.c')) arm_common_system_ss.add(files( 'arch_dump.c', + 'arm-powerctl.c', 'debug_helper.c', 'helper.c', 'vfp_fpscr.c', -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v8 27/48] target/arm/arm-powerctl: compile file once (system) 2025-05-12 18:04 ` [PATCH v8 27/48] target/arm/arm-powerctl: " Pierrick Bouvier @ 2025-05-13 10:07 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 71+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-13 10:07 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson On 12/5/25 20:04, Pierrick Bouvier wrote: > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/meson.build | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v8 28/48] target/arm/cortex-regs: compile file once (system) 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (26 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 27/48] target/arm/arm-powerctl: " Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 29/48] target/arm/ptw: replace target_ulong with int64_t Pierrick Bouvier ` (19 subsequent siblings) 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 7db573f4a97..6e0327b6f5b 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -16,7 +16,6 @@ arm_system_ss = ss.source_set() arm_common_system_ss = ss.source_set() arm_system_ss.add(files( 'arm-qmp-cmds.c', - 'cortex-regs.c', 'machine.c', 'ptw.c', )) @@ -38,6 +37,7 @@ arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files( arm_common_system_ss.add(files( 'arch_dump.c', 'arm-powerctl.c', + 'cortex-regs.c', 'debug_helper.c', 'helper.c', 'vfp_fpscr.c', -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v8 29/48] target/arm/ptw: replace target_ulong with int64_t 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (27 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 28/48] target/arm/cortex-regs: " Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-13 10:09 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 30/48] target/arm/ptw: replace TARGET_AARCH64 by CONFIG_ATOMIC64 from arm_casq_ptw Pierrick Bouvier ` (18 subsequent siblings) 47 siblings, 1 reply; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier sextract64 returns a signed value. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/ptw.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 89979c07e5a..68ec3f5e755 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1660,7 +1660,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, uint64_t ttbr; hwaddr descaddr, indexmask, indexmask_grainsize; uint32_t tableattrs; - target_ulong page_size; + uint64_t page_size; uint64_t attrs; int32_t stride; int addrsize, inputsize, outputsize; @@ -1733,7 +1733,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, * validation to do here. */ if (inputsize < addrsize) { - target_ulong top_bits = sextract64(address, inputsize, + uint64_t top_bits = sextract64(address, inputsize, addrsize - inputsize); if (-top_bits != param.select) { /* The gap between the two regions is a Translation fault */ -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v8 29/48] target/arm/ptw: replace target_ulong with int64_t 2025-05-12 18:04 ` [PATCH v8 29/48] target/arm/ptw: replace target_ulong with int64_t Pierrick Bouvier @ 2025-05-13 10:09 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 71+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-13 10:09 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson Hi Pierrick, On 12/5/25 20:04, Pierrick Bouvier wrote: > sextract64 returns a signed value. > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/ptw.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/arm/ptw.c b/target/arm/ptw.c > index 89979c07e5a..68ec3f5e755 100644 > --- a/target/arm/ptw.c > +++ b/target/arm/ptw.c > @@ -1660,7 +1660,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, > uint64_t ttbr; > hwaddr descaddr, indexmask, indexmask_grainsize; > uint32_t tableattrs; > - target_ulong page_size; > + uint64_t page_size; Subject mentions int64_t, description mentions signed, but patch uses unsigned uint64_t, is that expected? > uint64_t attrs; > int32_t stride; > int addrsize, inputsize, outputsize; > @@ -1733,7 +1733,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, > * validation to do here. > */ > if (inputsize < addrsize) { > - target_ulong top_bits = sextract64(address, inputsize, > + uint64_t top_bits = sextract64(address, inputsize, > addrsize - inputsize); > if (-top_bits != param.select) { > /* The gap between the two regions is a Translation fault */ ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v8 30/48] target/arm/ptw: replace TARGET_AARCH64 by CONFIG_ATOMIC64 from arm_casq_ptw 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (28 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 29/48] target/arm/ptw: replace target_ulong with int64_t Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-13 10:41 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 31/48] target/arm/ptw: compile file once (system) Pierrick Bouvier ` (17 subsequent siblings) 47 siblings, 1 reply; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier This function needs 64 bit compare exchange, so we hide implementation for hosts not supporting it (some 32 bit target, which don't run 64 bit guests anyway). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/ptw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 68ec3f5e755..44170d831cc 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -737,7 +737,7 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, uint64_t new_val, S1Translate *ptw, ARMMMUFaultInfo *fi) { -#if defined(TARGET_AARCH64) && defined(CONFIG_TCG) +#if defined(CONFIG_ATOMIC64) && defined(CONFIG_TCG) uint64_t cur_val; void *host = ptw->out_host; -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v8 30/48] target/arm/ptw: replace TARGET_AARCH64 by CONFIG_ATOMIC64 from arm_casq_ptw 2025-05-12 18:04 ` [PATCH v8 30/48] target/arm/ptw: replace TARGET_AARCH64 by CONFIG_ATOMIC64 from arm_casq_ptw Pierrick Bouvier @ 2025-05-13 10:41 ` Philippe Mathieu-Daudé 2025-05-13 17:03 ` Richard Henderson 0 siblings, 1 reply; 71+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-13 10:41 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson On 12/5/25 20:04, Pierrick Bouvier wrote: > This function needs 64 bit compare exchange, so we hide implementation > for hosts not supporting it (some 32 bit target, which don't run 64 bit > guests anyway). > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/ptw.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/ptw.c b/target/arm/ptw.c > index 68ec3f5e755..44170d831cc 100644 > --- a/target/arm/ptw.c > +++ b/target/arm/ptw.c > @@ -737,7 +737,7 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, > uint64_t new_val, S1Translate *ptw, > ARMMMUFaultInfo *fi) > { > -#if defined(TARGET_AARCH64) && defined(CONFIG_TCG) > +#if defined(CONFIG_ATOMIC64) && defined(CONFIG_TCG) > uint64_t cur_val; > void *host = ptw->out_host; > I'd feel safer squashing: -- >8 -- @@ -743,2 +743,5 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, + /* AArch32 does not have FEAT_HADFS */ + assert(cpu_isar_feature(aa64_hafs, env_archcpu(env))); + if (unlikely(!host)) { @@ -854,3 +857,3 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, #else - /* AArch32 does not have FEAT_HADFS; non-TCG guests only use debug-mode. */ + /* non-TCG guests only use debug-mode. */ g_assert_not_reached(); --- With that: Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v8 30/48] target/arm/ptw: replace TARGET_AARCH64 by CONFIG_ATOMIC64 from arm_casq_ptw 2025-05-13 10:41 ` Philippe Mathieu-Daudé @ 2025-05-13 17:03 ` Richard Henderson 2025-05-13 17:12 ` Philippe Mathieu-Daudé 0 siblings, 1 reply; 71+ messages in thread From: Richard Henderson @ 2025-05-13 17:03 UTC (permalink / raw) To: Philippe Mathieu-Daudé, Pierrick Bouvier, qemu-devel Cc: kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini On 5/13/25 03:41, Philippe Mathieu-Daudé wrote: > On 12/5/25 20:04, Pierrick Bouvier wrote: >> This function needs 64 bit compare exchange, so we hide implementation >> for hosts not supporting it (some 32 bit target, which don't run 64 bit >> guests anyway). >> >> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> >> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> >> --- >> target/arm/ptw.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/target/arm/ptw.c b/target/arm/ptw.c >> index 68ec3f5e755..44170d831cc 100644 >> --- a/target/arm/ptw.c >> +++ b/target/arm/ptw.c >> @@ -737,7 +737,7 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, >> uint64_t new_val, S1Translate *ptw, >> ARMMMUFaultInfo *fi) >> { >> -#if defined(TARGET_AARCH64) && defined(CONFIG_TCG) >> +#if defined(CONFIG_ATOMIC64) && defined(CONFIG_TCG) >> uint64_t cur_val; >> void *host = ptw->out_host; > > I'd feel safer squashing: > > -- >8 -- > @@ -743,2 +743,5 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, > > + /* AArch32 does not have FEAT_HADFS */ > + assert(cpu_isar_feature(aa64_hafs, env_archcpu(env))); Why? This is checked in the setting of param.{ha,hd}. See aa{32,64}_va_parameters. r~ ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v8 30/48] target/arm/ptw: replace TARGET_AARCH64 by CONFIG_ATOMIC64 from arm_casq_ptw 2025-05-13 17:03 ` Richard Henderson @ 2025-05-13 17:12 ` Philippe Mathieu-Daudé 2025-05-14 6:12 ` Richard Henderson 0 siblings, 1 reply; 71+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-13 17:12 UTC (permalink / raw) To: Richard Henderson, Pierrick Bouvier, qemu-devel Cc: kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini On 13/5/25 19:03, Richard Henderson wrote: > On 5/13/25 03:41, Philippe Mathieu-Daudé wrote: >> On 12/5/25 20:04, Pierrick Bouvier wrote: >>> This function needs 64 bit compare exchange, so we hide implementation >>> for hosts not supporting it (some 32 bit target, which don't run 64 bit >>> guests anyway). >>> >>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> >>> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> >>> --- >>> target/arm/ptw.c | 2 +- >>> 1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/target/arm/ptw.c b/target/arm/ptw.c >>> index 68ec3f5e755..44170d831cc 100644 >>> --- a/target/arm/ptw.c >>> +++ b/target/arm/ptw.c >>> @@ -737,7 +737,7 @@ static uint64_t arm_casq_ptw(CPUARMState *env, >>> uint64_t old_val, >>> uint64_t new_val, S1Translate *ptw, >>> ARMMMUFaultInfo *fi) >>> { >>> -#if defined(TARGET_AARCH64) && defined(CONFIG_TCG) >>> +#if defined(CONFIG_ATOMIC64) && defined(CONFIG_TCG) >>> uint64_t cur_val; >>> void *host = ptw->out_host; >> >> I'd feel safer squashing: >> >> -- >8 -- >> @@ -743,2 +743,5 @@ static uint64_t arm_casq_ptw(CPUARMState *env, >> uint64_t old_val, >> >> + /* AArch32 does not have FEAT_HADFS */ >> + assert(cpu_isar_feature(aa64_hafs, env_archcpu(env))); > > Why? This is checked in the setting of param.{ha,hd}. > See aa{32,64}_va_parameters. I suppose the "AArch32 does not have FEAT_HADFS" is misleading then. Better if no changes are necessary and this series can go as is. ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v8 30/48] target/arm/ptw: replace TARGET_AARCH64 by CONFIG_ATOMIC64 from arm_casq_ptw 2025-05-13 17:12 ` Philippe Mathieu-Daudé @ 2025-05-14 6:12 ` Richard Henderson 0 siblings, 0 replies; 71+ messages in thread From: Richard Henderson @ 2025-05-14 6:12 UTC (permalink / raw) To: Philippe Mathieu-Daudé, Pierrick Bouvier, qemu-devel Cc: kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini On 5/13/25 18:12, Philippe Mathieu-Daudé wrote: > On 13/5/25 19:03, Richard Henderson wrote: >> On 5/13/25 03:41, Philippe Mathieu-Daudé wrote: >>> + /* AArch32 does not have FEAT_HADFS */ >>> + assert(cpu_isar_feature(aa64_hafs, env_archcpu(env))); >> >> Why? This is checked in the setting of param.{ha,hd}. >> See aa{32,64}_va_parameters. > > I suppose the "AArch32 does not have FEAT_HADFS" is misleading then. It isn't -- aa32_va_parameters does not set param.{ha,hd}. r~ ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v8 31/48] target/arm/ptw: compile file once (system) 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (29 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 30/48] target/arm/ptw: replace TARGET_AARCH64 by CONFIG_ATOMIC64 from arm_casq_ptw Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 32/48] target/arm/meson: accelerator files are not needed in user mode Pierrick Bouvier ` (16 subsequent siblings) 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 6e0327b6f5b..151184da71c 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -17,7 +17,6 @@ arm_common_system_ss = ss.source_set() arm_system_ss.add(files( 'arm-qmp-cmds.c', 'machine.c', - 'ptw.c', )) arm_user_ss = ss.source_set() @@ -40,6 +39,7 @@ arm_common_system_ss.add(files( 'cortex-regs.c', 'debug_helper.c', 'helper.c', + 'ptw.c', 'vfp_fpscr.c', )) -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v8 32/48] target/arm/meson: accelerator files are not needed in user mode 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (30 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 31/48] target/arm/ptw: compile file once (system) Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-13 10:10 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 33/48] target/arm/kvm-stub: compile file once (system) Pierrick Bouvier ` (15 subsequent siblings) 47 siblings, 1 reply; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/meson.build | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 151184da71c..29a36fb3c5e 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -5,9 +5,6 @@ arm_ss.add(files( )) arm_ss.add(zlib) -arm_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c'), if_false: files('kvm-stub.c')) -arm_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) - arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'cpu64.c', 'gdbstub64.c')) @@ -18,6 +15,8 @@ arm_system_ss.add(files( 'arm-qmp-cmds.c', 'machine.c', )) +arm_system_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c'), if_false: files('kvm-stub.c')) +arm_system_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) arm_user_ss = ss.source_set() arm_user_ss.add(files('cpu.c')) -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v8 32/48] target/arm/meson: accelerator files are not needed in user mode 2025-05-12 18:04 ` [PATCH v8 32/48] target/arm/meson: accelerator files are not needed in user mode Pierrick Bouvier @ 2025-05-13 10:10 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 71+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-13 10:10 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson On 12/5/25 20:04, Pierrick Bouvier wrote: > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/meson.build | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v8 33/48] target/arm/kvm-stub: compile file once (system) 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (31 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 32/48] target/arm/meson: accelerator files are not needed in user mode Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 34/48] target/arm/machine: reduce migration include to avoid target specific definitions Pierrick Bouvier ` (14 subsequent siblings) 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/meson.build | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 29a36fb3c5e..bb1c09676d5 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -15,7 +15,7 @@ arm_system_ss.add(files( 'arm-qmp-cmds.c', 'machine.c', )) -arm_system_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c'), if_false: files('kvm-stub.c')) +arm_system_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c')) arm_system_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) arm_user_ss = ss.source_set() @@ -32,6 +32,7 @@ arm_user_ss.add(files( arm_common_system_ss.add(files('cpu.c'), capstone) arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files( 'cpu32-stubs.c')) +arm_common_system_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) arm_common_system_ss.add(files( 'arch_dump.c', 'arm-powerctl.c', -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v8 34/48] target/arm/machine: reduce migration include to avoid target specific definitions 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (32 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 33/48] target/arm/kvm-stub: compile file once (system) Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-13 10:43 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 35/48] target/arm/machine: remove TARGET_AARCH64 from migration state Pierrick Bouvier ` (13 subsequent siblings) 47 siblings, 1 reply; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/machine.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/machine.c b/target/arm/machine.c index 978249fb71b..f7956898fa1 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -6,7 +6,8 @@ #include "kvm_arm.h" #include "internals.h" #include "cpu-features.h" -#include "migration/cpu.h" +#include "migration/qemu-file-types.h" +#include "migration/vmstate.h" #include "target/arm/gtimer.h" static bool vfp_needed(void *opaque) -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v8 34/48] target/arm/machine: reduce migration include to avoid target specific definitions 2025-05-12 18:04 ` [PATCH v8 34/48] target/arm/machine: reduce migration include to avoid target specific definitions Pierrick Bouvier @ 2025-05-13 10:43 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 71+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-13 10:43 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson On 12/5/25 20:04, Pierrick Bouvier wrote: > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/machine.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/target/arm/machine.c b/target/arm/machine.c > index 978249fb71b..f7956898fa1 100644 > --- a/target/arm/machine.c > +++ b/target/arm/machine.c > @@ -6,7 +6,8 @@ > #include "kvm_arm.h" > #include "internals.h" > #include "cpu-features.h" > -#include "migration/cpu.h" > +#include "migration/qemu-file-types.h" > +#include "migration/vmstate.h" Ah indeed I did the same for microblaze. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v8 35/48] target/arm/machine: remove TARGET_AARCH64 from migration state 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (33 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 34/48] target/arm/machine: reduce migration include to avoid target specific definitions Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-13 10:10 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 36/48] target/arm/machine: move cpu_post_load kvm bits to kvm_arm_cpu_post_load function Pierrick Bouvier ` (12 subsequent siblings) 47 siblings, 1 reply; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier This exposes two new subsections for arm: vmstate_sve and vmstate_za. Those sections have a ".needed" callback, which already allow to skip them when not needed. vmstate_sve .needed is checking cpu_isar_feature(aa64_sve, cpu). vmstate_za .needed is checking ZA flag in cpu->env.svcr. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/machine.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/target/arm/machine.c b/target/arm/machine.c index f7956898fa1..868246a98c0 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -241,7 +241,6 @@ static const VMStateDescription vmstate_iwmmxt = { } }; -#ifdef TARGET_AARCH64 /* The expression ARM_MAX_VQ - 2 is 0 for pure AArch32 build, * and ARMPredicateReg is actively empty. This triggers errors * in the expansion of the VMSTATE macros. @@ -321,7 +320,6 @@ static const VMStateDescription vmstate_za = { VMSTATE_END_OF_LIST() } }; -#endif /* AARCH64 */ static bool serror_needed(void *opaque) { @@ -1102,10 +1100,8 @@ const VMStateDescription vmstate_arm_cpu = { &vmstate_pmsav7, &vmstate_pmsav8, &vmstate_m_security, -#ifdef TARGET_AARCH64 &vmstate_sve, &vmstate_za, -#endif &vmstate_serror, &vmstate_irq_line_state, &vmstate_wfxt_timer, -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v8 35/48] target/arm/machine: remove TARGET_AARCH64 from migration state 2025-05-12 18:04 ` [PATCH v8 35/48] target/arm/machine: remove TARGET_AARCH64 from migration state Pierrick Bouvier @ 2025-05-13 10:10 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 71+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-13 10:10 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson On 12/5/25 20:04, Pierrick Bouvier wrote: > This exposes two new subsections for arm: vmstate_sve and vmstate_za. > Those sections have a ".needed" callback, which already allow to skip > them when not needed. > > vmstate_sve .needed is checking cpu_isar_feature(aa64_sve, cpu). > vmstate_za .needed is checking ZA flag in cpu->env.svcr. > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/machine.c | 4 ---- > 1 file changed, 4 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v8 36/48] target/arm/machine: move cpu_post_load kvm bits to kvm_arm_cpu_post_load function 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (34 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 35/48] target/arm/machine: remove TARGET_AARCH64 from migration state Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-13 10:45 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 37/48] target/arm/kvm-stub: add missing stubs Pierrick Bouvier ` (11 subsequent siblings) 47 siblings, 1 reply; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/kvm_arm.h | 4 +++- target/arm/kvm.c | 13 ++++++++++++- target/arm/machine.c | 8 +------- 3 files changed, 16 insertions(+), 9 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index b638e09a687..c4178d1327c 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -83,8 +83,10 @@ void kvm_arm_cpu_pre_save(ARMCPU *cpu); * @cpu: ARMCPU * * Called from cpu_post_load() to update KVM CPU state from the cpreg list. + * + * Returns: true on success, or false if write_list_to_kvmstate failed. */ -void kvm_arm_cpu_post_load(ARMCPU *cpu); +bool kvm_arm_cpu_post_load(ARMCPU *cpu); /** * kvm_arm_reset_vcpu: diff --git a/target/arm/kvm.c b/target/arm/kvm.c index b6c39ca61fa..a08a269ad61 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -938,13 +938,24 @@ void kvm_arm_cpu_pre_save(ARMCPU *cpu) } } -void kvm_arm_cpu_post_load(ARMCPU *cpu) +bool kvm_arm_cpu_post_load(ARMCPU *cpu) { + if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) { + return false; + } + /* Note that it's OK for the TCG side not to know about + * every register in the list; KVM is authoritative if + * we're using it. + */ + write_list_to_cpustate(cpu); + /* KVM virtual time adjustment */ if (cpu->kvm_adjvtime) { cpu->kvm_vtime = *kvm_arm_get_cpreg_ptr(cpu, KVM_REG_ARM_TIMER_CNT); cpu->kvm_vtime_dirty = true; } + + return true; } void kvm_arm_reset_vcpu(ARMCPU *cpu) diff --git a/target/arm/machine.c b/target/arm/machine.c index 868246a98c0..e442d485241 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -976,15 +976,9 @@ static int cpu_post_load(void *opaque, int version_id) } if (kvm_enabled()) { - if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) { + if (!kvm_arm_cpu_post_load(cpu)) { return -1; } - /* Note that it's OK for the TCG side not to know about - * every register in the list; KVM is authoritative if - * we're using it. - */ - write_list_to_cpustate(cpu); - kvm_arm_cpu_post_load(cpu); } else { if (!write_list_to_cpustate(cpu)) { return -1; -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v8 36/48] target/arm/machine: move cpu_post_load kvm bits to kvm_arm_cpu_post_load function 2025-05-12 18:04 ` [PATCH v8 36/48] target/arm/machine: move cpu_post_load kvm bits to kvm_arm_cpu_post_load function Pierrick Bouvier @ 2025-05-13 10:45 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 71+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-13 10:45 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson On 12/5/25 20:04, Pierrick Bouvier wrote: > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/kvm_arm.h | 4 +++- > target/arm/kvm.c | 13 ++++++++++++- > target/arm/machine.c | 8 +------- > 3 files changed, 16 insertions(+), 9 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v8 37/48] target/arm/kvm-stub: add missing stubs 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (35 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 36/48] target/arm/machine: move cpu_post_load kvm bits to kvm_arm_cpu_post_load function Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 38/48] target/arm/machine: compile file once (system) Pierrick Bouvier ` (10 subsequent siblings) 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Those become needed once kvm_enabled can't be known at compile time. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/kvm-stub.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c index 4806365cdc5..34e57fab011 100644 --- a/target/arm/kvm-stub.c +++ b/target/arm/kvm-stub.c @@ -109,3 +109,13 @@ void arm_cpu_kvm_set_irq(void *arm_cpu, int irq, int level) { g_assert_not_reached(); } + +void kvm_arm_cpu_pre_save(ARMCPU *cpu) +{ + g_assert_not_reached(); +} + +bool kvm_arm_cpu_post_load(ARMCPU *cpu) +{ + g_assert_not_reached(); +} -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v8 38/48] target/arm/machine: compile file once (system) 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (36 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 37/48] target/arm/kvm-stub: add missing stubs Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-13 10:11 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 39/48] target/arm/tcg/vec_internal: use forward declaration for CPUARMState Pierrick Bouvier ` (9 subsequent siblings) 47 siblings, 1 reply; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index bb1c09676d5..b404fa54863 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -13,7 +13,6 @@ arm_system_ss = ss.source_set() arm_common_system_ss = ss.source_set() arm_system_ss.add(files( 'arm-qmp-cmds.c', - 'machine.c', )) arm_system_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c')) arm_system_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) @@ -39,6 +38,7 @@ arm_common_system_ss.add(files( 'cortex-regs.c', 'debug_helper.c', 'helper.c', + 'machine.c', 'ptw.c', 'vfp_fpscr.c', )) -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v8 38/48] target/arm/machine: compile file once (system) 2025-05-12 18:04 ` [PATCH v8 38/48] target/arm/machine: compile file once (system) Pierrick Bouvier @ 2025-05-13 10:11 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 71+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-13 10:11 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson On 12/5/25 20:04, Pierrick Bouvier wrote: > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/meson.build | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v8 39/48] target/arm/tcg/vec_internal: use forward declaration for CPUARMState 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (37 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 38/48] target/arm/machine: compile file once (system) Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 40/48] target/arm/tcg/crypto_helper: compile file once Pierrick Bouvier ` (8 subsequent siblings) 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Needed so this header can be included without requiring cpu.h. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/tcg/vec_internal.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/tcg/vec_internal.h b/target/arm/tcg/vec_internal.h index 6b93b5aeb94..c02f9c37f83 100644 --- a/target/arm/tcg/vec_internal.h +++ b/target/arm/tcg/vec_internal.h @@ -22,6 +22,8 @@ #include "fpu/softfloat.h" +typedef struct CPUArchState CPUARMState; + /* * Note that vector data is stored in host-endian 64-bit chunks, * so addressing units smaller than that needs a host-endian fixup. -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v8 40/48] target/arm/tcg/crypto_helper: compile file once 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (38 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 39/48] target/arm/tcg/vec_internal: use forward declaration for CPUARMState Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 41/48] target/arm/tcg/hflags: compile file twice (system, user) Pierrick Bouvier ` (7 subsequent siblings) 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/tcg/crypto_helper.c | 6 ++++-- target/arm/tcg/meson.build | 5 ++++- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c index 7cadd61e124..3428bd1bf0b 100644 --- a/target/arm/tcg/crypto_helper.c +++ b/target/arm/tcg/crypto_helper.c @@ -10,14 +10,16 @@ */ #include "qemu/osdep.h" +#include "qemu/bitops.h" -#include "cpu.h" -#include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "crypto/aes-round.h" #include "crypto/sm4.h" #include "vec_internal.h" +#define HELPER_H "tcg/helper.h" +#include "exec/helper-proto.h.inc" + union CRYPTO_STATE { uint8_t bytes[16]; uint32_t words[4]; diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index dd12ccedb18..2f73eefe383 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -30,7 +30,6 @@ arm_ss.add(files( 'translate-mve.c', 'translate-neon.c', 'translate-vfp.c', - 'crypto_helper.c', 'hflags.c', 'iwmmxt_helper.c', 'm_helper.c', @@ -63,3 +62,7 @@ arm_system_ss.add(files( arm_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c')) arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c')) + +arm_common_ss.add(files( + 'crypto_helper.c', +)) -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v8 41/48] target/arm/tcg/hflags: compile file twice (system, user) 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (39 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 40/48] target/arm/tcg/crypto_helper: compile file once Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 42/48] target/arm/tcg/iwmmxt_helper: " Pierrick Bouvier ` (6 subsequent siblings) 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/tcg/hflags.c | 4 +++- target/arm/tcg/meson.build | 8 +++++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index fd407a7b28e..1ccec63bbd4 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -9,11 +9,13 @@ #include "cpu.h" #include "internals.h" #include "cpu-features.h" -#include "exec/helper-proto.h" #include "exec/translation-block.h" #include "accel/tcg/cpu-ops.h" #include "cpregs.h" +#define HELPER_H "tcg/helper.h" +#include "exec/helper-proto.h.inc" + static inline bool fgt_svc(CPUARMState *env, int el) { /* diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 2f73eefe383..cee00b24cda 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -30,7 +30,6 @@ arm_ss.add(files( 'translate-mve.c', 'translate-neon.c', 'translate-vfp.c', - 'hflags.c', 'iwmmxt_helper.c', 'm_helper.c', 'mve_helper.c', @@ -66,3 +65,10 @@ arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c')) arm_common_ss.add(files( 'crypto_helper.c', )) + +arm_common_system_ss.add(files( + 'hflags.c', +)) +arm_user_ss.add(files( + 'hflags.c', +)) -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v8 42/48] target/arm/tcg/iwmmxt_helper: compile file twice (system, user) 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (40 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 41/48] target/arm/tcg/hflags: compile file twice (system, user) Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 43/48] target/arm/tcg/neon_helper: " Pierrick Bouvier ` (5 subsequent siblings) 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/tcg/iwmmxt_helper.c | 4 +++- target/arm/tcg/meson.build | 3 ++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/iwmmxt_helper.c b/target/arm/tcg/iwmmxt_helper.c index 610b1b2103e..ba054b6b4db 100644 --- a/target/arm/tcg/iwmmxt_helper.c +++ b/target/arm/tcg/iwmmxt_helper.c @@ -22,7 +22,9 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/helper-proto.h" + +#define HELPER_H "tcg/helper.h" +#include "exec/helper-proto.h.inc" /* iwMMXt macros extracted from GNU gdb. */ diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index cee00b24cda..02dfe768c5d 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -30,7 +30,6 @@ arm_ss.add(files( 'translate-mve.c', 'translate-neon.c', 'translate-vfp.c', - 'iwmmxt_helper.c', 'm_helper.c', 'mve_helper.c', 'neon_helper.c', @@ -68,7 +67,9 @@ arm_common_ss.add(files( arm_common_system_ss.add(files( 'hflags.c', + 'iwmmxt_helper.c', )) arm_user_ss.add(files( 'hflags.c', + 'iwmmxt_helper.c', )) -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v8 43/48] target/arm/tcg/neon_helper: compile file twice (system, user) 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (41 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 42/48] target/arm/tcg/iwmmxt_helper: " Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 44/48] target/arm/tcg/tlb_helper: " Pierrick Bouvier ` (4 subsequent siblings) 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/tcg/neon_helper.c | 4 +++- target/arm/tcg/meson.build | 3 ++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/neon_helper.c b/target/arm/tcg/neon_helper.c index e2cc7cf4ee6..2cc8241f1e4 100644 --- a/target/arm/tcg/neon_helper.c +++ b/target/arm/tcg/neon_helper.c @@ -9,11 +9,13 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "vec_internal.h" +#define HELPER_H "tcg/helper.h" +#include "exec/helper-proto.h.inc" + #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 02dfe768c5d..af786196d2f 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -32,7 +32,6 @@ arm_ss.add(files( 'translate-vfp.c', 'm_helper.c', 'mve_helper.c', - 'neon_helper.c', 'op_helper.c', 'tlb_helper.c', 'vec_helper.c', @@ -68,8 +67,10 @@ arm_common_ss.add(files( arm_common_system_ss.add(files( 'hflags.c', 'iwmmxt_helper.c', + 'neon_helper.c', )) arm_user_ss.add(files( 'hflags.c', 'iwmmxt_helper.c', + 'neon_helper.c', )) -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v8 44/48] target/arm/tcg/tlb_helper: compile file twice (system, user) 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (42 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 43/48] target/arm/tcg/neon_helper: " Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 45/48] target/arm/helper: restrict define_tlb_insn_regs to system target Pierrick Bouvier ` (3 subsequent siblings) 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/tcg/tlb_helper.c | 3 ++- target/arm/tcg/meson.build | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index d9e6c827d43..23c72a99f5c 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -9,8 +9,9 @@ #include "cpu.h" #include "internals.h" #include "cpu-features.h" -#include "exec/helper-proto.h" +#define HELPER_H "tcg/helper.h" +#include "exec/helper-proto.h.inc" /* * Returns true if the stage 1 translation regime is using LPAE format page diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index af786196d2f..49c8f4390a1 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -33,7 +33,6 @@ arm_ss.add(files( 'm_helper.c', 'mve_helper.c', 'op_helper.c', - 'tlb_helper.c', 'vec_helper.c', 'tlb-insns.c', 'arith_helper.c', @@ -68,9 +67,11 @@ arm_common_system_ss.add(files( 'hflags.c', 'iwmmxt_helper.c', 'neon_helper.c', + 'tlb_helper.c', )) arm_user_ss.add(files( 'hflags.c', 'iwmmxt_helper.c', 'neon_helper.c', + 'tlb_helper.c', )) -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v8 45/48] target/arm/helper: restrict define_tlb_insn_regs to system target 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (43 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 44/48] target/arm/tcg/tlb_helper: " Pierrick Bouvier @ 2025-05-12 18:04 ` Pierrick Bouvier 2025-05-12 18:05 ` [PATCH v8 46/48] target/arm/tcg/tlb-insns: compile file once (system) Pierrick Bouvier ` (2 subsequent siblings) 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:04 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Allows to include target/arm/tcg/tlb-insns.c only for system targets. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index aae8554e8f2..76312102879 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7764,7 +7764,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, not_v8_cp_reginfo); } +#ifndef CONFIG_USER_ONLY define_tlb_insn_regs(cpu); +#endif if (arm_feature(env, ARM_FEATURE_V6)) { /* The ID registers all have impdef reset values */ -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v8 46/48] target/arm/tcg/tlb-insns: compile file once (system) 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (44 preceding siblings ...) 2025-05-12 18:04 ` [PATCH v8 45/48] target/arm/helper: restrict define_tlb_insn_regs to system target Pierrick Bouvier @ 2025-05-12 18:05 ` Pierrick Bouvier 2025-05-13 10:12 ` Philippe Mathieu-Daudé 2025-05-12 18:05 ` [PATCH v8 47/48] target/arm/tcg/arith_helper: compile file once Pierrick Bouvier 2025-05-12 18:05 ` [PATCH v8 48/48] target/arm/tcg/vfp_helper: compile file twice (system, user) Pierrick Bouvier 47 siblings, 1 reply; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:05 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier aarch64 specific code is guarded by cpu_isar_feature(aa64*), so it's safe to expose it. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/tcg/tlb-insns.c | 7 ------- target/arm/tcg/meson.build | 2 +- 2 files changed, 1 insertion(+), 8 deletions(-) diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c index 0407ad5542d..95c26c6d463 100644 --- a/target/arm/tcg/tlb-insns.c +++ b/target/arm/tcg/tlb-insns.c @@ -35,7 +35,6 @@ static CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri, return CP_ACCESS_OK; } -#ifdef TARGET_AARCH64 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */ static CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -46,7 +45,6 @@ static CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *ri, } return CP_ACCESS_OK; } -#endif /* IS variants of TLB operations must affect all cores */ static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -802,7 +800,6 @@ static const ARMCPRegInfo tlbi_el3_cp_reginfo[] = { .writefn = tlbi_aa64_vae3_write }, }; -#ifdef TARGET_AARCH64 typedef struct { uint64_t base; uint64_t length; @@ -1270,8 +1267,6 @@ static const ARMCPRegInfo tlbi_rme_reginfo[] = { .writefn = tlbi_aa64_paallos_write }, }; -#endif - void define_tlb_insn_regs(ARMCPU *cpu) { CPUARMState *env = &cpu->env; @@ -1299,7 +1294,6 @@ void define_tlb_insn_regs(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_EL3)) { define_arm_cp_regs(cpu, tlbi_el3_cp_reginfo); } -#ifdef TARGET_AARCH64 if (cpu_isar_feature(aa64_tlbirange, cpu)) { define_arm_cp_regs(cpu, tlbirange_reginfo); } @@ -1309,5 +1303,4 @@ void define_tlb_insn_regs(ARMCPU *cpu) if (cpu_isar_feature(aa64_rme, cpu)) { define_arm_cp_regs(cpu, tlbi_rme_reginfo); } -#endif } diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 49c8f4390a1..5d326585401 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -34,7 +34,6 @@ arm_ss.add(files( 'mve_helper.c', 'op_helper.c', 'vec_helper.c', - 'tlb-insns.c', 'arith_helper.c', 'vfp_helper.c', )) @@ -68,6 +67,7 @@ arm_common_system_ss.add(files( 'iwmmxt_helper.c', 'neon_helper.c', 'tlb_helper.c', + 'tlb-insns.c', )) arm_user_ss.add(files( 'hflags.c', -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v8 46/48] target/arm/tcg/tlb-insns: compile file once (system) 2025-05-12 18:05 ` [PATCH v8 46/48] target/arm/tcg/tlb-insns: compile file once (system) Pierrick Bouvier @ 2025-05-13 10:12 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 71+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-13 10:12 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson On 12/5/25 20:05, Pierrick Bouvier wrote: > aarch64 specific code is guarded by cpu_isar_feature(aa64*), so it's > safe to expose it. > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/tcg/tlb-insns.c | 7 ------- > target/arm/tcg/meson.build | 2 +- > 2 files changed, 1 insertion(+), 8 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v8 47/48] target/arm/tcg/arith_helper: compile file once 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (45 preceding siblings ...) 2025-05-12 18:05 ` [PATCH v8 46/48] target/arm/tcg/tlb-insns: compile file once (system) Pierrick Bouvier @ 2025-05-12 18:05 ` Pierrick Bouvier 2025-05-12 18:05 ` [PATCH v8 48/48] target/arm/tcg/vfp_helper: compile file twice (system, user) Pierrick Bouvier 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:05 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/tcg/arith_helper.c | 5 +++-- target/arm/tcg/meson.build | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/arith_helper.c b/target/arm/tcg/arith_helper.c index 9a555c7966c..670139819df 100644 --- a/target/arm/tcg/arith_helper.c +++ b/target/arm/tcg/arith_helper.c @@ -6,11 +6,12 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ #include "qemu/osdep.h" -#include "cpu.h" -#include "exec/helper-proto.h" #include "qemu/crc32c.h" #include <zlib.h> /* for crc32 */ +#define HELPER_H "tcg/helper.h" +#include "exec/helper-proto.h.inc" + /* * Note that signed overflow is undefined in C. The following routines are * careful to use unsigned types where modulo arithmetic is required. diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 5d326585401..7502c5cded6 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -34,7 +34,6 @@ arm_ss.add(files( 'mve_helper.c', 'op_helper.c', 'vec_helper.c', - 'arith_helper.c', 'vfp_helper.c', )) @@ -59,6 +58,7 @@ arm_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c')) arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c')) arm_common_ss.add(files( + 'arith_helper.c', 'crypto_helper.c', )) -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v8 48/48] target/arm/tcg/vfp_helper: compile file twice (system, user) 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier ` (46 preceding siblings ...) 2025-05-12 18:05 ` [PATCH v8 47/48] target/arm/tcg/arith_helper: compile file once Pierrick Bouvier @ 2025-05-12 18:05 ` Pierrick Bouvier 47 siblings, 0 replies; 71+ messages in thread From: Pierrick Bouvier @ 2025-05-12 18:05 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, kvm, alex.bennee, anjo, qemu-arm, Peter Maydell, Paolo Bonzini, Richard Henderson, Pierrick Bouvier Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/tcg/vfp_helper.c | 4 +++- target/arm/tcg/meson.build | 3 ++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/vfp_helper.c b/target/arm/tcg/vfp_helper.c index b32e2f4e27c..b1324c5c0a6 100644 --- a/target/arm/tcg/vfp_helper.c +++ b/target/arm/tcg/vfp_helper.c @@ -19,12 +19,14 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/helper-proto.h" #include "internals.h" #include "cpu-features.h" #include "fpu/softfloat.h" #include "qemu/log.h" +#define HELPER_H "tcg/helper.h" +#include "exec/helper-proto.h.inc" + /* * Set the float_status behaviour to match the Arm defaults: * * tininess-before-rounding diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 7502c5cded6..2d1502ba882 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -34,7 +34,6 @@ arm_ss.add(files( 'mve_helper.c', 'op_helper.c', 'vec_helper.c', - 'vfp_helper.c', )) arm_ss.add(when: 'TARGET_AARCH64', if_true: files( @@ -68,10 +67,12 @@ arm_common_system_ss.add(files( 'neon_helper.c', 'tlb_helper.c', 'tlb-insns.c', + 'vfp_helper.c', )) arm_user_ss.add(files( 'hflags.c', 'iwmmxt_helper.c', 'neon_helper.c', 'tlb_helper.c', + 'vfp_helper.c', )) -- 2.47.2 ^ permalink raw reply related [flat|nested] 71+ messages in thread
end of thread, other threads:[~2025-05-14 6:12 UTC | newest] Thread overview: 71+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-05-12 18:04 [PATCH v8 00/48] single-binary: compile target/arm twice Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 01/48] target/arm: Replace target_ulong -> vaddr for HWBreakpoint Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 02/48] include/system/hvf: missing vaddr include Pierrick Bouvier 2025-05-13 9:58 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 03/48] meson: add common libs for target and target_system Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 04/48] target/arm: move kvm stubs and remove CONFIG_KVM from kvm_arm.h Pierrick Bouvier 2025-05-13 9:58 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 05/48] target/arm/kvm-stub: add kvm_arm_reset_vcpu stub Pierrick Bouvier 2025-05-13 10:00 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 06/48] target/arm/cpu: move arm_cpu_kvm_set_irq to kvm.c Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 07/48] target/arm/cpu: remove TARGET_BIG_ENDIAN dependency Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 08/48] target/arm/cpu: remove TARGET_AARCH64 around aarch64_cpu_dump_state common Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 09/48] target/arm/cpu: remove TARGET_AARCH64 in arm_cpu_finalize_features Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 10/48] target/arm/cpu: compile file twice (user, system) only Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 11/48] target/arm/cpu32-stubs.c: compile file twice (user, system) Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 12/48] tcg: add vaddr type for helpers Pierrick Bouvier 2025-05-13 10:03 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 13/48] target/arm/helper: use vaddr instead of target_ulong for exception_pc_alignment Pierrick Bouvier 2025-05-13 10:03 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 14/48] target/arm/helper: use vaddr instead of target_ulong for probe_access Pierrick Bouvier 2025-05-13 10:04 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 15/48] target/arm/helper: extract common helpers Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 16/48] target/arm/debug_helper: only include " Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 17/48] target/arm/debug_helper: remove target_ulong Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 18/48] target/arm/debug_helper: compile file twice (user, system) Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 19/48] target/arm/helper: restrict include to common helpers Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 20/48] target/arm/helper: replace target_ulong by vaddr Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 21/48] target/arm/helper: expose aarch64 cpu registration Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 22/48] target/arm/helper: remove remaining TARGET_AARCH64 Pierrick Bouvier 2025-05-13 10:06 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 23/48] target/arm/helper: compile file twice (user, system) Pierrick Bouvier 2025-05-13 10:06 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 24/48] target/arm/vfp_fpscr: " Pierrick Bouvier 2025-05-13 10:07 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 25/48] target/arm/arch_dump: remove TARGET_AARCH64 conditionals Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 26/48] target/arm/arch_dump: compile file once (system) Pierrick Bouvier 2025-05-13 10:07 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 27/48] target/arm/arm-powerctl: " Pierrick Bouvier 2025-05-13 10:07 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 28/48] target/arm/cortex-regs: " Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 29/48] target/arm/ptw: replace target_ulong with int64_t Pierrick Bouvier 2025-05-13 10:09 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 30/48] target/arm/ptw: replace TARGET_AARCH64 by CONFIG_ATOMIC64 from arm_casq_ptw Pierrick Bouvier 2025-05-13 10:41 ` Philippe Mathieu-Daudé 2025-05-13 17:03 ` Richard Henderson 2025-05-13 17:12 ` Philippe Mathieu-Daudé 2025-05-14 6:12 ` Richard Henderson 2025-05-12 18:04 ` [PATCH v8 31/48] target/arm/ptw: compile file once (system) Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 32/48] target/arm/meson: accelerator files are not needed in user mode Pierrick Bouvier 2025-05-13 10:10 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 33/48] target/arm/kvm-stub: compile file once (system) Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 34/48] target/arm/machine: reduce migration include to avoid target specific definitions Pierrick Bouvier 2025-05-13 10:43 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 35/48] target/arm/machine: remove TARGET_AARCH64 from migration state Pierrick Bouvier 2025-05-13 10:10 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 36/48] target/arm/machine: move cpu_post_load kvm bits to kvm_arm_cpu_post_load function Pierrick Bouvier 2025-05-13 10:45 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 37/48] target/arm/kvm-stub: add missing stubs Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 38/48] target/arm/machine: compile file once (system) Pierrick Bouvier 2025-05-13 10:11 ` Philippe Mathieu-Daudé 2025-05-12 18:04 ` [PATCH v8 39/48] target/arm/tcg/vec_internal: use forward declaration for CPUARMState Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 40/48] target/arm/tcg/crypto_helper: compile file once Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 41/48] target/arm/tcg/hflags: compile file twice (system, user) Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 42/48] target/arm/tcg/iwmmxt_helper: " Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 43/48] target/arm/tcg/neon_helper: " Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 44/48] target/arm/tcg/tlb_helper: " Pierrick Bouvier 2025-05-12 18:04 ` [PATCH v8 45/48] target/arm/helper: restrict define_tlb_insn_regs to system target Pierrick Bouvier 2025-05-12 18:05 ` [PATCH v8 46/48] target/arm/tcg/tlb-insns: compile file once (system) Pierrick Bouvier 2025-05-13 10:12 ` Philippe Mathieu-Daudé 2025-05-12 18:05 ` [PATCH v8 47/48] target/arm/tcg/arith_helper: compile file once Pierrick Bouvier 2025-05-12 18:05 ` [PATCH v8 48/48] target/arm/tcg/vfp_helper: compile file twice (system, user) Pierrick Bouvier
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