From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kash Pande Subject: Re: [PATCH v4 2/5] target/i386: Populate AMD Processor Cache Information Date: Wed, 21 Mar 2018 13:12:39 -0400 Message-ID: References: <1520888449-4352-1-git-send-email-babu.moger@amd.com> <1520888449-4352-3-git-send-email-babu.moger@amd.com> <20180316180006.GH28578@localhost.localdomain> <20180320175427.GU3417@localhost.localdomain> <20180321170941.GX3417@localhost.localdomain> Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="RFWpB8MRhmgDzFuKgIb9FNYZIGt2Tvr3I" Cc: "Lendacky, Thomas" , "Singh, Brijesh" , "kvm@vger.kernel.org" , "rkrcmar@redhat.com" , "mtosatti@redhat.com" , "Hook, Gary" , "qemu-devel@nongnu.org" , "pbonzini@redhat.com" , "rth@twiddle.net" To: Eduardo Habkost , "Moger, Babu" Return-path: In-Reply-To: <20180321170941.GX3417@localhost.localdomain> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+gceq-qemu-devel2=m.gmane.org@nongnu.org Sender: "Qemu-devel" List-Id: kvm.vger.kernel.org This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --RFWpB8MRhmgDzFuKgIb9FNYZIGt2Tvr3I From: Kash Pande To: Eduardo Habkost , "Moger, Babu" Cc: "pbonzini@redhat.com" , "rth@twiddle.net" , "rkrcmar@redhat.com" , "Lendacky, Thomas" , "Singh, Brijesh" , "kvm@vger.kernel.org" , "mtosatti@redhat.com" , "Hook, Gary" , "qemu-devel@nongnu.org" Message-ID: Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD Processor Cache Information References: <1520888449-4352-1-git-send-email-babu.moger@amd.com> <1520888449-4352-3-git-send-email-babu.moger@amd.com> <20180316180006.GH28578@localhost.localdomain> <20180320175427.GU3417@localhost.localdomain> <20180321170941.GX3417@localhost.localdomain> In-Reply-To: <20180321170941.GX3417@localhost.localdomain> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On 2018-03-21 01:09 PM, Eduardo Habkost wrote: > This makes sense if you want to change a CPU model to enable > topoext by default. But I suggest setting it for > ("EPYC" "-" TYPE_X86_CPU) only, not TYPE_X86_CPU, as EPYC is the > only CPU model affected by patch 4/5. AIUI, all 17h CPUs have TOPOEXT and SMT support. I've been in contact with Babu to have the patches extended to more general use case. Kash --RFWpB8MRhmgDzFuKgIb9FNYZIGt2Tvr3I Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- iQFIBAEBCAAyFiEE5MQWwRLWQeWW1A0MLHWyk7icJXgFAlqykosUHGthc2hAdHJp cGxlYmFjay5uZXQACgkQLHWyk7icJXhCJgf+KMh+nGBvPkYjbsbSTFtt5QyD+LG1 EyIbfDEwCLXjgOY4c2+Usb+HxgFWbdE11mfNK5fi5pktrBc3LvifSlmolAv+KZMb bN22JDwkyVDVdsTelN2epc3rvRIhTtgoz16VnvnL6S0id9XDenDNddpx8O4jqTQO gKDxqpDjQaV/jZD68s3p8GeP38336zyj+4P05sMdXio5mtwT15oTPUgFYjrAs1PD MAKFkxjJ+2g5fHSzE7YOZwZvU2UE8NaEIRrdl+jpeHcDrM/9EKqFYepnxeP1rlO8 t9pDgvZiU6sG9Mptg6CilogiGHrOUZv0SKBrHuX+ALvKnx+tN770wwCrFg== =vCRC -----END PGP SIGNATURE----- --RFWpB8MRhmgDzFuKgIb9FNYZIGt2Tvr3I--