Re: [PATCH v9 04/10] x86,fs/resctrl: Implement "io_alloc" enable/disable handlers

["Moger, Babu" <bmoger@amd.com>]

Hi Reinette,

On 9/18/2025 12:19 AM, Reinette Chatre wrote:
> Hi Babu,
> 
> On 9/2/25 3:41 PM, Babu Moger wrote:
>> "io_alloc" enables direct insertion of data from I/O devices into the
>> cache.
> 
> (repetition)
> 
>>
>> On AMD systems, "io_alloc" feature is backed by L3 Smart Data Cache
>> Injection Allocation Enforcement (SDCIAE). Change SDCIAE state by setting
>> (to enable) or clearing (to disable) bit 1 of MSR L3_QOS_EXT_CFG on all
> 
> Did you notice Boris's touchup on ABMC "x86/resctrl: Add data structures and
> definitions for ABMC assignment"? This should be MSR_IA32_L3_QOS_EXT_CFG
> (also needed in patch self, more below)

Yes.

>> logical processors within the cache domain.
>>
>> Introduce architecture-specific call to enable and disable the feature.
>>
>> The SDCIAE feature details are documented in APM [1] available from [2].
>> [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming
>> Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache
>> Injection Allocation Enforcement (SDCIAE)
> 
> (same comment as patch #1)
> 
> Changelog that aims to address feeback received in ABMC series, please feel free
> to improve:
> 	"io_alloc" is the generic name of the new resctrl feature that enables
> 	system software to configure the portion of cache allocated for I/O
> 	traffic. On AMD systems, "io_alloc" resctrl feature is backed by AMD's
> 	L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE).
>                                                                                  
> 	Introduce the architecture-specific functions that resctrl fs should call
> 	to enable, disable, or check status of the "io_alloc" feature. Change
> 	SDCIAE state by setting (to enable) or clearing (to disable) bit 1 of
>   	MSR_IA32_L3_QOS_EXT_CFG on all logical processors within the cache domain.
>                                                                                  
> 	The SDCIAE feature details are documented in APM [1] available from [2].
> 	[1] AMD64 Architecture Programmer's Manual Volume 2: System Programming
> 	    Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache
> 	    Injection Allocation Enforcement (SDCIAE)
> 

Looks good. Thanks
>>
>> Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 # [2]
> 
> (please move to end of tags)

Sure.

> 
>> Signed-off-by: Babu Moger <babu.moger@amd.com>
>> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
>> ---
> 
> ...
> 
>> +static void _resctrl_sdciae_enable(struct rdt_resource *r, bool enable)
>> +{
>> +	struct rdt_ctrl_domain *d;
>> +
>> +	/* Walking r->ctrl_domains, ensure it can't race with cpuhp */
>> +	lockdep_assert_cpus_held();
>> +
>> +	/* Update L3_QOS_EXT_CFG MSR on all the CPUs in all domains */
> 
> "L3_QOS_EXT_CFG MSR" -> MSR_IA32_L3_QOS_EXT_CFG
> 
> (to match touchups needed to ABMC series)

Yes.

> 
>> +	list_for_each_entry(d, &r->ctrl_domains, hdr.list)
>> +		on_each_cpu_mask(&d->hdr.cpu_mask, resctrl_sdciae_set_one_amd, &enable, 1);
>> +}
>> +
>> +int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable)
>> +{
>> +	struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
>> +
>> +	if (hw_res->r_resctrl.cache.io_alloc_capable &&
>> +	    hw_res->sdciae_enabled != enable) {
>> +		_resctrl_sdciae_enable(r, enable);
>> +		hw_res->sdciae_enabled = enable;
>> +	}
>> +
>> +	return 0;
>> +}
>> diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h
>> index 5e3c41b36437..70f5317f1ce4 100644
>> --- a/arch/x86/kernel/cpu/resctrl/internal.h
>> +++ b/arch/x86/kernel/cpu/resctrl/internal.h
>> @@ -37,6 +37,9 @@ struct arch_mbm_state {
>>   	u64	prev_msr;
>>   };
>>   
>> +/* Setting bit 1 in L3_QOS_EXT_CFG enables the SDCIAE feature. */
> 
> "L3_QOS_EXT_CFG" -> MSR_IA32_L3_QOS_EXT_CFG
> 
Sure.
Thanks
Babu