Re: [PATCH v15 04/13] x86/sev: Change TSC MSR behavior for Secure TSC enabled guests

[Nikunj A Dadhania <nikunj@amd.com>]

On 12/10/2024 7:59 PM, Tom Lendacky wrote:
> On 12/9/24 23:02, Nikunj A. Dadhania wrote:
>> On 12/9/2024 9:27 PM, Borislav Petkov wrote:
>>> On Tue, Dec 03, 2024 at 02:30:36PM +0530, Nikunj A Dadhania wrote:
>>> +
>>> +	if (write) {
>>> +		WARN_ONCE(1, "TSC MSR writes are verboten!\n");
>>> +		return ES_UNSUPPORTED;
>>
>> Sure, we can add a WARN_ONCE().
> 
> You'll want to test this... IIRC, I'm not sure if a WARN_ONCE() will be
> properly printed when issued within the #VC handler (since it will
> generate a nested #VC).

Right, a write to TSC MSR generates the following splat:

[   17.450076] ------------[ cut here ]------------
[   17.450077] TSC MSR writes are verboten!
[   17.450079] WARNING: CPU: 0 PID: 617 at arch/x86/coco/sev/core.c:1456 vc_handle_exitcode.part.0+0xe54/0x1110
[   17.450090] CPU: 0 UID: 0 PID: 617 Comm: wrmsr Tainted: G S                 6.13.0-rc1-00093-g5e3143d631a9-dirty #121


Regards,
Nikunj