From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06B6B262FF6; Tue, 16 Sep 2025 07:20:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758007233; cv=none; b=C4h1zPxuOoulFxtSBLS+/9RMxGBxxMcUSnzTk5bqFvwpZGUc+y/7Grc4rpQlNRonEgHt+9dHxxe4KvloCeCPZKWupUWGMRICWWBe7fBrv2mL5V9H4yIpunmSeViDXuxfIP3fNfjkOfBn2PRS9k/Cg0pf8KrgTlIgxNrRSSCS2IQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758007233; c=relaxed/simple; bh=37Fy6N+KfsDikO4TqwR4OWfPbZGWzuU4xuF6iKlsq8Y=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=EDMCoBPWBBq6fdhBCUa+H9ZBxMwUtRHLQLAlzleAHx/4QqvqxTu83wCUqdXyy/YUbmdJHEHeMpQhGMdiAJzqpXm+PAXQp6JLiw7rYgUFupWypToAJxSgX/OgmnIgxhX26rqVVoKZ+wOM2NhjDV3odnc2RKjf3T0aGSOkaDQoKRc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=l6IQULo+; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="l6IQULo+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1758007232; x=1789543232; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=37Fy6N+KfsDikO4TqwR4OWfPbZGWzuU4xuF6iKlsq8Y=; b=l6IQULo+rAGkpyjBOgzjvIisqWGZah+LeYiwLySiGxaRYbgWTTbsfUep mCwXDSUoz0ganH9gLvdbniuZS+svOMrXMpWgxUsJUq0sEksHDqz77RmnI q1nzFsOGeRLf1FKptrbyK+qsfC52eUsTqt7tW00NaDcn40XpK0Rf5fLSP 9oabLWjbSp6eDfoB/2xFlUQebh+f2bpoydGRv9YKrLK1G5Va3IBKErAkG 4pmuiozprA/wNAfoWhKSZoJGQ39XoJAa2HLNdwispveI3yaNr464Za0nr R+3vWsrcr7H1Bcsh5k3PyIni+i4IOyqwfbg5FmuCKx0LsPGNpjqkXK+3x w==; X-CSE-ConnectionGUID: 8OU0KaHLQuSZ10thYvh2RA== X-CSE-MsgGUID: pDtg81EtT2S4FzYxPI+Yjg== X-IronPort-AV: E=McAfee;i="6800,10657,11554"; a="71704915" X-IronPort-AV: E=Sophos;i="6.18,268,1751266800"; d="scan'208";a="71704915" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2025 00:20:31 -0700 X-CSE-ConnectionGUID: W4Z+oqg6TPqTeg691iEvkQ== X-CSE-MsgGUID: bohQPtd2QFiN9wRdst0C6w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,268,1751266800"; d="scan'208";a="205644703" Received: from unknown (HELO [10.238.0.107]) ([10.238.0.107]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2025 00:20:29 -0700 Message-ID: Date: Tue, 16 Sep 2025 15:20:26 +0800 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v15 06/41] KVM: x86: Check XSS validity against guest CPUIDs To: Sean Christopherson Cc: Paolo Bonzini , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Tom Lendacky , Mathias Krause , John Allen , Rick Edgecombe , Chao Gao , Maxim Levitsky , Xiaoyao Li , Zhang Yi Z References: <20250912232319.429659-1-seanjc@google.com> <20250912232319.429659-7-seanjc@google.com> Content-Language: en-US From: Binbin Wu In-Reply-To: <20250912232319.429659-7-seanjc@google.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 9/13/2025 7:22 AM, Sean Christopherson wrote: > From: Chao Gao > > Maintain per-guest valid XSS bits and check XSS validity against them > rather than against KVM capabilities. This is to prevent bits that are > supported by KVM but not supported for a guest from being set. > > Opportunistically return KVM_MSR_RET_UNSUPPORTED on IA32_XSS MSR accesses > if guest CPUID doesn't enumerate X86_FEATURE_XSAVES. Since > KVM_MSR_RET_UNSUPPORTED takes care of host_initiated cases, drop the > host_initiated check. > > Signed-off-by: Chao Gao > Reviewed-by: Xiaoyao Li > Signed-off-by: Sean Christopherson Reviewed-by: Binbin Wu > --- > arch/x86/include/asm/kvm_host.h | 3 ++- > arch/x86/kvm/cpuid.c | 12 ++++++++++++ > arch/x86/kvm/x86.c | 7 +++---- > 3 files changed, 17 insertions(+), 5 deletions(-) > > diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h > index 2762554cbb7b..d931d72d23c9 100644 > --- a/arch/x86/include/asm/kvm_host.h > +++ b/arch/x86/include/asm/kvm_host.h > @@ -815,7 +815,6 @@ struct kvm_vcpu_arch { > bool at_instruction_boundary; > bool tpr_access_reporting; > bool xfd_no_write_intercept; > - u64 ia32_xss; > u64 microcode_version; > u64 arch_capabilities; > u64 perf_capabilities; > @@ -876,6 +875,8 @@ struct kvm_vcpu_arch { > > u64 xcr0; > u64 guest_supported_xcr0; > + u64 ia32_xss; > + u64 guest_supported_xss; > > struct kvm_pio_request pio; > void *pio_data; > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c > index ad6cadf09930..46cf616663e6 100644 > --- a/arch/x86/kvm/cpuid.c > +++ b/arch/x86/kvm/cpuid.c > @@ -263,6 +263,17 @@ static u64 cpuid_get_supported_xcr0(struct kvm_vcpu *vcpu) > return (best->eax | ((u64)best->edx << 32)) & kvm_caps.supported_xcr0; > } > > +static u64 cpuid_get_supported_xss(struct kvm_vcpu *vcpu) > +{ > + struct kvm_cpuid_entry2 *best; > + > + best = kvm_find_cpuid_entry_index(vcpu, 0xd, 1); > + if (!best) > + return 0; > + > + return (best->ecx | ((u64)best->edx << 32)) & kvm_caps.supported_xss; > +} > + > static __always_inline void kvm_update_feature_runtime(struct kvm_vcpu *vcpu, > struct kvm_cpuid_entry2 *entry, > unsigned int x86_feature, > @@ -424,6 +435,7 @@ void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) > } > > vcpu->arch.guest_supported_xcr0 = cpuid_get_supported_xcr0(vcpu); > + vcpu->arch.guest_supported_xss = cpuid_get_supported_xss(vcpu); > > vcpu->arch.pv_cpuid.features = kvm_apply_cpuid_pv_features_quirk(vcpu); > > diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c > index 3b4258b38ad8..5a5af40c06a9 100644 > --- a/arch/x86/kvm/x86.c > +++ b/arch/x86/kvm/x86.c > @@ -3984,15 +3984,14 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) > } > break; > case MSR_IA32_XSS: > - if (!msr_info->host_initiated && > - !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) > - return 1; > + if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) > + return KVM_MSR_RET_UNSUPPORTED; > /* > * KVM supports exposing PT to the guest, but does not support > * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than > * XSAVES/XRSTORS to save/restore PT MSRs. > */ > - if (data & ~kvm_caps.supported_xss) > + if (data & ~vcpu->arch.guest_supported_xss) > return 1; > vcpu->arch.ia32_xss = data; > vcpu->arch.cpuid_dynamic_bits_dirty = true;