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[16.163.40.128]) by smtp.gmail.com with ESMTPSA id d4-20020a17090ac24400b002a2fe0998f0sm54885pjx.19.2024.04.04.06.45.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 04 Apr 2024 06:45:14 -0700 (PDT) Message-ID: Date: Thu, 4 Apr 2024 21:45:05 +0800 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 00/15] Coalesced Interrupt Delivery with posted MSI Content-Language: en-US To: Jacob Pan , LKML , X86 Kernel , Peter Zijlstra , iommu@lists.linux.dev, Thomas Gleixner , Lu Baolu , kvm@vger.kernel.org, Dave Hansen , Joerg Roedel , "H. Peter Anvin" , Borislav Petkov , Ingo Molnar Cc: Paul Luse , Dan Williams , Jens Axboe , Raj Ashok , "Tian, Kevin" , maz@kernel.org, seanjc@google.com, Robin Murphy References: <20240126234237.547278-1-jacob.jun.pan@linux.intel.com> From: Robert Hoo In-Reply-To: <20240126234237.547278-1-jacob.jun.pan@linux.intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 1/27/2024 7:42 AM, Jacob Pan wrote: > Hi Thomas and all, > > This patch set is aimed to improve IRQ throughput on Intel Xeon by making use of > posted interrupts. > > There is a session at LPC2023 IOMMU/VFIO/PCI MC where I have presented this > topic. > > https://lpc.events/event/17/sessions/172/#20231115 > > Background > ========== > On modern x86 server SoCs, interrupt remapping (IR) is required and turned > on by default to support X2APIC. Two interrupt remapping modes can be supported > by IOMMU/VT-d: > > - Remappable (host) > - Posted (guest only so far) > > With remappable mode, the device MSI to CPU process is a HW flow without system > software touch points, it roughly goes as follows: > > 1. Devices issue interrupt requests with writes to 0xFEEx_xxxx > 2. The system agent accepts and remaps/translates the IRQ > 3. Upon receiving the translation response, the system agent notifies the > destination CPU with the translated MSI > 4. CPU's local APIC accepts interrupts into its IRR/ISR registers > 5. Interrupt delivered through IDT (MSI vector) > > The above process can be inefficient under high IRQ rates. The notifications in > step #3 are often unnecessary when the destination CPU is already overwhelmed > with handling bursts of IRQs. On some architectures, such as Intel Xeon, step #3 > is also expensive and requires strong ordering w.r.t DMA. Can you tell more on this "step #3 requires strong ordering w.r.t. DMA"? > As a result, slower > IRQ rates can become a limiting factor for DMA I/O performance. >