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* [PATCH v8 0/2] Enable Secure TSC for SEV-SNP
@ 2025-07-07 10:10 Nikunj A Dadhania
  2025-07-07 10:10 ` [PATCH v8 1/2] x86/cpufeatures: Add SNP Secure TSC Nikunj A Dadhania
  2025-07-07 10:10 ` [PATCH v8 2/2] KVM: SVM: Enable Secure TSC for SNP guests Nikunj A Dadhania
  0 siblings, 2 replies; 23+ messages in thread
From: Nikunj A Dadhania @ 2025-07-07 10:10 UTC (permalink / raw)
  To: seanjc, pbonzini, kvm
  Cc: thomas.lendacky, santosh.shukla, bp, nikunj, isaku.yamahata,
	vaishali.thakkar, kai.huang

The hypervisor controls TSC value calculations for the guest. A malicious
hypervisor can prevent the guest from progressing. The Secure TSC feature for
SEV-SNP allows guests to securely use the RDTSC and RDTSCP instructions. This
ensures the guest has a consistent view of time and prevents a malicious
hypervisor from manipulating time, such as making it appear to move backward or
advance too quickly. For more details, refer to the "Secure Nested Paging
(SEV-SNP)" section, subsection "Secure TSC" in APM Volume 2.

Patches are based on kvm-x86/next which includes MSR interception rework and a
fix adding missing desired_tsc_khz to struct sev_data_snp_launch_start

51a4273dcab3 ("KVM: SVM: Add missing member in SNP_LAUNCH_START command structure")

Testing Secure TSC
-----------------

Secure TSC guest patches are available as part of v6.14.

QEMU changes:
https://github.com/nikunjad/qemu/tree/snp-securetsc-latest

QEMU command line SEV-SNP with Secure TSC:

  qemu-system-x86_64 -cpu EPYC-Milan-v2 -smp 4 \
    -object memory-backend-memfd,id=ram1,size=1G,share=true,prealloc=false,reserve=false \
    -object sev-snp-guest,id=sev0,cbitpos=51,reduced-phys-bits=1,secure-tsc=on,stsc-freq=2000000000 \
    -machine q35,confidential-guest-support=sev0,memory-backend=ram1 \
    ...

Changelog:
----------
v8:
* Commit message improvements (Kai Huang)
* Remove 'desired_tsc_khz' from 'struct Kim_sev_snp_launch_start' (Kai Huang)

v7: https://lore.kernel.org/kvm/20250630104426.13812-1-nikunj@amd.com/

* Rebased on top of kvm-x86/next that has MSR interception rework
* As snp_secure_tsc_enabled() is used only in sev.c, move it there (Sean) 
* Add checks to prevent user-triggerable WARN_ON_ONCE (Sean)
* Squash GUEST_TSC_FREQ MSR addition patch
* Dropped RB/TB as patch 3/4 got changed

Nikunj A Dadhania (2):
  x86/cpufeatures: Add SNP Secure TSC
  KVM: SVM: Enable Secure TSC for SNP guests

 arch/x86/include/asm/cpufeatures.h |  1 +
 arch/x86/include/asm/svm.h         |  1 +
 arch/x86/kvm/svm/sev.c             | 34 +++++++++++++++++++++++++++---
 3 files changed, 33 insertions(+), 3 deletions(-)


base-commit: 6c7ecd725e503bf2ca69ff52c6cc48bb650b1f11
-- 
2.43.0


^ permalink raw reply	[flat|nested] 23+ messages in thread

end of thread, other threads:[~2025-07-10 23:30 UTC | newest]

Thread overview: 23+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-07-07 10:10 [PATCH v8 0/2] Enable Secure TSC for SEV-SNP Nikunj A Dadhania
2025-07-07 10:10 ` [PATCH v8 1/2] x86/cpufeatures: Add SNP Secure TSC Nikunj A Dadhania
2025-07-07 10:10 ` [PATCH v8 2/2] KVM: SVM: Enable Secure TSC for SNP guests Nikunj A Dadhania
2025-07-07 13:34   ` Tom Lendacky
2025-07-08  2:21   ` Huang, Kai
2025-07-08  6:45     ` Nikunj A. Dadhania
2025-07-08 10:48       ` Huang, Kai
2025-07-08 14:34         ` Sean Christopherson
2025-07-08 22:42           ` Huang, Kai
2025-07-09  4:14           ` Nikunj A. Dadhania
2025-07-08  7:16     ` Xiaoyao Li
2025-07-08 10:53       ` Huang, Kai
2025-07-08 14:42         ` Sean Christopherson
2025-07-08 22:56           ` Huang, Kai
2025-07-08 23:08             ` Sean Christopherson
2025-07-09  5:54               ` Huang, Kai
2025-07-08 14:37   ` Sean Christopherson
2025-07-09  4:12     ` Nikunj A. Dadhania
2025-07-09 13:02       ` Sean Christopherson
2025-07-10 10:59         ` Nikunj A Dadhania
2025-07-10 13:20           ` Sean Christopherson
2025-07-10 15:04             ` Nikunj A. Dadhania
2025-07-10 23:30               ` Sean Christopherson

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