Re: [PATCH v6 0/6] target/i386: Update EPYC CPU models for Cache property, RAS, SVM feature and add EPYC-Turin CPU model

["Moger, Babu" <bmoger@amd.com>]

Hi Paolo,

On 3/7/2025 4:47 PM, Moger, Babu wrote:
> Hi Paolo,
> 
> Can you please pull these series if you don't have any concerns.
> 
> Thanks
> Babu
> 
> On 2/28/2025 12:07 PM, Babu Moger wrote:
>>
>> Following changes are implemented in this series.
>>
>> 1. Fixed the cache(L2,L3) property details in all the EPYC models.
>> 2. Add RAS feature bits (SUCCOR, McaOverflowRecov) on all EPYC models
>> 3. Add missing SVM feature bits required for nested guests on all EPYC 
>> models
>> 4. Add the missing feature bit fs-gs-base-ns(WRMSR to {FS,GS,KERNEL_G} 
>> S_BASE is
>>     non-serializing). This bit is added in EPYC-Genoa and EPYC-Turin 
>> models.
>> 5. Add RAS, SVM, fs-gs-base-ns and perfmon-v2 on EPYC-Genoa and EPYC- 
>> Turin models.
>> 6. Add support for EPYC-Turin.
>>     (Add all the above feature bits and few additional bits movdiri, 
>> movdir64b,
>>      avx512-vp2intersect, avx-vnni, sbpb, ibpb-brtype, srso-user- 
>> kernel-no).
>>
>> Link: https://www.amd.com/content/dam/amd/en/documents/epyc-technical- 
>> docs/programmer-references/57238.zip
>> Link: https://www.amd.com/content/dam/amd/en/documents/corporate/cr/ 
>> speculative-return-stack-overflow-whitepaper.pdf
>> ---
>> v6: Initialized the boolean feature bits to true where applicable.
>>      Added Reviewed-by tag from Zhao.
>>
>> v5: Add EPYC-Turin CPU model
>>      Dropped ERAPS and RAPSIZE bits from EPYC-Turin models as kernel 
>> support for
>>      these bits are not done yet. Users can still use the options 
>> +eraps,+rapsize
>>      to test these featers.
>>      Add Reviewed-by tag from Maksim for the patches already reviewed.
>>
>> v4: Some of the patches in v3 are already merged. Posting the rest of 
>> the patches.
>>      Dropped EPYC-Turin model for now. Will post them later.
>>      Added SVM feature bit as discussed in
>>      https://lore.kernel.org/kvm/b4b7abae-669a-4a86-81d3- 
>> d1f677a82929@redhat.com/
>>      Fixed the cache property details as discussed in
>>      https://lore.kernel.org/kvm/20230504205313.225073-8- 
>> babu.moger@amd.com/
>>      Thanks to Maksim and Paolo for their feedback.
>>
>> v3: Added SBPB, IBPB_BRTYPE, SRSO_USER_KERNEL_NO, ERAPS and RAPSIZE bits
>>      to EPYC-Turin.
>>      Added new patch(1) to fix a minor typo.
>>
>> v2: Fixed couple of typos.
>>      Added Reviewed-by tag from Zhao.
>>      Rebased on top of 6d00c6f98256 ("Merge tag 'for-upstream' of 
>> https://repo.or.cz/qemu/kevin into staging")
>>
>> Previous revisions:
>> v5: https://lore.kernel.org/kvm/cover.1738869208.git.babu.moger@amd.com/
>> v4: https://lore.kernel.org/kvm/cover.1731616198.git.babu.moger@amd.com/
>> v3: https://lore.kernel.org/kvm/cover.1729807947.git.babu.moger@amd.com/
>> v2: https://lore.kernel.org/kvm/cover.1723068946.git.babu.moger@amd.com/
>> v1: https://lore.kernel.org/qemu-devel/ 
>> cover.1718218999.git.babu.moger@amd.com/
>>
>> Babu Moger (6):
>>    target/i386: Update EPYC CPU model for Cache property, RAS, SVM
>>      feature bits
>>    target/i386: Update EPYC-Rome CPU model for Cache property, RAS, SVM
>>      feature bits
>>    target/i386: Update EPYC-Milan CPU model for Cache property, RAS, SVM
>>      feature bits
>>    target/i386: Add feature that indicates WRMSR to BASE reg is
>>      non-serializing
>>    target/i386: Update EPYC-Genoa for Cache property, perfmon-v2, RAS and
>>      SVM feature bits
>>    target/i386: Add support for EPYC-Turin model
>>
>>   target/i386/cpu.c | 437 +++++++++++++++++++++++++++++++++++++++++++++-
>>   target/i386/cpu.h |   2 +
>>   2 files changed, 438 insertions(+), 1 deletion(-)
>>
> 

Gently ping again. We are waiting for these patches to be picked up in 
the next merge cycle. Let me know if you have any concerns.

Thanks
Babu