Re: [PATCH v2 1/2] KVM: nVMX: don't check PIR.ON when processing nested posted interrupts

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] x86/kvm: direct usage of __smp_mb__after_atomic() bypasses KCSAN
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commit b3864bd32325846a2ccca43a4ce66f3b92dcb341
Author: Maxim Levitsky <mlevitsk@redhat.com>

KVM: nVMX: don't check PIR.ON when processing nested posted interrupts
    
Despite the suggestion to test and set the PIR.ON and avoid sending
a posted interrupt if it is already set, there is no requirement
for this bit to be set for posted interrupt processing to happen
when the target CPU receives the posted notification vector.

> diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
> index ddf6df7bee93b..50548e3483181 100644
> --- a/arch/x86/kvm/vmx/nested.c
> +++ b/arch/x86/kvm/vmx/nested.c
> @@ -4033,8 +4033,16 @@ static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
>  
>  	vmx->nested.pi_pending = false;
>  
> -	if (!pi_test_and_clear_on(vmx->nested.pi_desc))
> -		return 0;
> +	/*
> +	 * Don't test the value of PID.ON.
> +	 * It is valid to trigger a posted interrupt without setting this bit
> +	 */
> +	pi_clear_on(vmx->nested.pi_desc);
> +
> +	/* Ensure that guests sees the change to PIR.ON before KVM harvest
> +	 * the PIR
> +	 */
> +	__smp_mb__after_atomic();

[Severity: Low]
Does this code intentionally bypass KCSAN instrumentation?

By calling the architecture-internal macro __smp_mb__after_atomic() directly
instead of the generic smp_mb__after_atomic() API, KCSAN instrumentation
(provided by kcsan_mb()) is skipped.

While this does not cause a functional memory ordering bug on x86, it violates
kernel API conventions and could lead to false positives when running KCSAN.

>  
>  	max_irr = pi_find_highest_vector(vmx->nested.pi_desc);
>  	if (max_irr > 0) {

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Sashiko AI review · https://sashiko.dev/#/patchset/20261011001303.723721-1-mlevitsk@redhat.com?part=1