From: sashiko-bot@kernel.org
To: "Sascha Bischoff" <sascha.bischoff@arm.com>,
kvmarm@lists.linux.dev, kvm@vger.kernel.org
Cc: "Oliver Upton" <oupton@kernel.org>, "Marc Zyngier" <maz@kernel.org>
Subject: Re: [PATCH v2 09/16] KVM: arm64: gic-v5: Add ITS MSI injection
Date: Mon, 02 Nov 2026 20:38:01 +0000 [thread overview]
Message-ID: <sashiko-outbox-194134@kernel.org> (raw)
In-Reply-To: <20261102194454.4086911-10-sascha.bischoff@arm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] KVM: arm64: gic-v5: missing vgic_initialized() check in MSI injection
--
commit b2f7c0263871635da8ddb0614e8b96f1cb1f641c
Author: Sascha Bischoff <sascha.bischoff@arm.com>
KVM: arm64: gic-v5: Add ITS MSI injection
This commit adds MSI injection support for the virtual GICv5 ITS via both
the slow guest-memory translation path and the inatomic cached translation
path. It wires kvm_set_msi() and kvm_arch_set_irq_inatomic() to invoke the
new GICv5 ITS injection helpers for GICv5 VMs.
> diff --git a/arch/arm64/kvm/vgic/vgic-its-v5.c b/arch/arm64/kvm/vgic/vgic-its-v5.c
> index 9f4783b243221..b69a1d107c0ae 100644
> --- a/arch/arm64/kvm/vgic/vgic-its-v5.c
> +++ b/arch/arm64/kvm/vgic/vgic-its-v5.c
[ ... ]
> @@ -424,12 +468,86 @@ static int __vgic_v5_its_resolve_lpi(struct kvm *kvm, struct vgic_v5_its *its,
> return ret;
> }
>
> +int vgic_v5_its_resolve_lpi(struct kvm *kvm, struct vgic_v5_its *its,
> + u32 device_id, u32 event_id,
> + struct vgic_irq **irq)
> +{
> + guard(mutex)(&its->its_lock);
> +
> + return __vgic_v5_its_resolve_lpi(kvm, its, device_id, event_id, irq);
> +}
> +
> static void vgic_v5_its_inject_lpi(struct kvm *kvm, struct vgic_irq *irq)
> {
> kvm_call_hyp(__vgic_v5_vdpend, irq->intid, true,
> kvm->arch.vgic.gicv5_vm.vm_id);
> }
>
> +int vgic_v5_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi)
> +{
> + struct vgic_v5_its *its;
> + struct vgic_irq *irq;
> + bool borrowed_mm = false;
> + int ret;
> +
> + its = vgic_v5_msi_to_its(kvm, msi);
> + if (IS_ERR(its))
> + return PTR_ERR(its);
> +
> + /* An irqfd cache miss is resolved by a worker outside the VM's mm. */
> + if (current->mm != kvm->mm) {
> + if (WARN_ON_ONCE(current->mm || !(current->flags & PF_KTHREAD)))
> + return -EWOULDBLOCK;
> +
> + if (!mmget_not_zero(kvm->mm))
> + return -EFAULT;
> +
> + kthread_use_mm(kvm->mm);
> + borrowed_mm = true;
> + }
> +
> + ret = vgic_v5_its_resolve_lpi(kvm, its, msi->devid, msi->data, &irq);
> + if (borrowed_mm) {
> + kthread_unuse_mm(kvm->mm);
> + mmput(kvm->mm);
> + }
> +
> + if (ret < 0)
> + return ret;
> + /* KVM_SIGNAL_MSI reports guest translation failures as blocked MSIs. */
> + if (ret)
> + return 0;
> +
> + vgic_v5_its_inject_lpi(kvm, irq);
> + vgic_put_irq(kvm, irq);
> +
> + return 1;
> +}
> +
> +int vgic_v5_its_inject_cached_translation(struct kvm *kvm, struct kvm_msi *msi)
> +{
> + struct vgic_v5_its *its;
> + struct vgic_irq *irq;
> + int ret;
> +
> + its = vgic_v5_msi_to_its(kvm, msi);
> + if (IS_ERR(its))
> + return PTR_ERR(its);
> +
> + if (!READ_ONCE(its->enabled))
> + return -EWOULDBLOCK;
> +
> + ret = its_cache_look_up_translation(its, msi->devid, (u16)msi->data,
> + &irq);
> + if (ret)
> + return -EWOULDBLOCK;
> +
> + vgic_v5_its_inject_lpi(kvm, irq);
> + vgic_put_irq(kvm, irq);
> +
> + return 0;
> +}
[Severity: High]
Can userspace trigger vgic_v5_its_inject_lpi() before the GICv5 VM has been
initialized?
When a VM creates KVM_DEV_TYPE_ARM_VGIC_V5 and KVM_DEV_TYPE_ARM_VGIC_V5_ITS,
kvm_vgic_create() initializes kvm->arch.vgic.gicv5_vm.vm_id to
VGIC_V5_VM_ID_INVAL (-1), and a valid VM ID is only allocated later during
KVM_DEV_ARM_VGIC_CTRL_INIT via:
vgic_init()
vgic_v5_init()
vgic_v5_allocate_vm_id()
However, vgic_v5_register_its_iodev() registers the ITS on KVM_MMIO_BUS as
soon as KVM_VGIC_V5_ADDR_TYPE_ITS is set, and userspace register access
allows writing GICV5_ITS_CR0 (setting its->enabled = true),
GICV5_ITS_DT_CFGR, and GICV5_ITS_DT_BASER before vgic_init() is called.
If userspace invokes KVM_SIGNAL_MSI or triggers an irqfd before
KVM_DEV_ARM_VGIC_CTRL_INIT, neither __vgic_v5_its_resolve_lpi(),
vgic_v5_its_inject_msi(), nor vgic_v5_its_inject_cached_translation() checks
vgic_initialized(kvm). As a result, vgic_v5_its_inject_lpi() will pass
VGIC_V5_VM_ID_INVAL truncated to u16 (0xffff) to __vgic_v5_vdpend(), which
executes the hardware VDPEND instruction with an unallocated VM ID (or
targets another active VM using VM ID 0xffff).
Should the MSI resolution and injection paths check vgic_initialized(kvm)
before resolving translations or calling vgic_v5_its_inject_lpi()?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261102194454.4086911-1-sascha.bischoff@arm.com?part=9
next prev parent reply other threads:[~2026-11-02 20:38 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-02 19:44 [PATCH v2 00/16] KVM: arm64: Add GICv5 ITS support Sascha Bischoff
2026-11-02 19:44 ` [PATCH v2 01/16] KVM: arm64: vgic: Split out common LPI allocation Sascha Bischoff
2026-11-03 13:41 ` Fuad Tabba
2026-11-02 19:44 ` [PATCH v2 02/16] KVM: arm64: vgic: Pass opaque device pointer to ITS MMIO callbacks Sascha Bischoff
2026-11-03 13:42 ` Fuad Tabba
2026-11-02 19:44 ` [PATCH v2 03/16] KVM: arm64: gic-v5: Share CoreSight ID register emulation Sascha Bischoff
2026-11-03 13:43 ` Fuad Tabba
2026-11-03 20:37 ` Wei-Lin Chang
2026-11-02 19:44 ` [PATCH v2 04/16] irqchip/gic-v5: Add ITS MMIO register definitions Sascha Bischoff
2026-11-03 13:44 ` Fuad Tabba
2026-11-02 19:44 ` [PATCH v2 05/16] KVM: arm64: gic-v5: Add ITS device skeleton Sascha Bischoff
2026-11-02 20:08 ` sashiko-bot
2026-11-02 19:44 ` [PATCH v2 06/16] KVM: arm64: gic-v5: Add ITS MMIO state emulation Sascha Bischoff
2026-11-02 20:05 ` sashiko-bot
2026-11-03 13:48 ` Fuad Tabba
2026-11-04 2:27 ` Wei-Lin Chang
2026-11-02 19:44 ` [PATCH v2 07/16] KVM: arm64: gic-v5: Add ITS guest table translation emulation Sascha Bischoff
2026-11-02 20:23 ` sashiko-bot
2026-11-04 4:40 ` Wei-Lin Chang
2026-11-02 19:44 ` [PATCH v2 08/16] KVM: arm64: gic-v5: Add ITS translation cache maintenance Sascha Bischoff
2026-11-03 13:54 ` Fuad Tabba
2026-11-02 19:44 ` [PATCH v2 09/16] KVM: arm64: gic-v5: Add ITS MSI injection Sascha Bischoff
2026-11-02 20:38 ` sashiko-bot [this message]
2026-11-03 13:56 ` Fuad Tabba
2026-11-02 19:44 ` [PATCH v2 10/16] KVM: arm64: gic-v5: Add ITS userspace register access Sascha Bischoff
2026-11-02 20:52 ` sashiko-bot
2026-11-03 14:22 ` Fuad Tabba
2026-11-02 19:44 ` [PATCH v2 11/16] irqchip/gic-v5: Enable direct injection in ITS Sascha Bischoff
2026-11-02 20:57 ` sashiko-bot
2026-11-03 14:47 ` Fuad Tabba
2026-11-02 19:44 ` [PATCH v2 12/16] KVM: arm64: vgic: Move direct MSI support helper to common MMIO code Sascha Bischoff
2026-11-02 19:44 ` [PATCH v2 13/16] KVM: arm64: gic-v5: Implement irq forwarding Sascha Bischoff
2026-11-02 21:17 ` sashiko-bot
2026-11-03 15:29 ` Fuad Tabba
2026-11-02 19:44 ` [PATCH v2 14/16] KVM: selftests: Add VGICv5 ITS attribute tests Sascha Bischoff
2026-11-02 19:44 ` [PATCH v2 15/16] KVM: selftests: Add VGICv5 ITS translation cache tests Sascha Bischoff
2026-11-02 21:07 ` sashiko-bot
2026-11-03 16:02 ` Fuad Tabba
2026-11-02 19:44 ` [PATCH v2 16/16] KVM: arm64: gic-v5: Document ITS userspace ABI Sascha Bischoff
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=sashiko-outbox-194134@kernel.org \
--to=sashiko-bot@kernel.org \
--cc=kvm@vger.kernel.org \
--cc=kvmarm@lists.linux.dev \
--cc=maz@kernel.org \
--cc=oupton@kernel.org \
--cc=sascha.bischoff@arm.com \
--cc=sashiko-reviews@lists.linux.dev \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox