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Fri, 7 Nov 2025 04:24:17 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: A5KJubIeX4vZ Date: Fri, 07 Nov 2025 10:23:56 +0100 From: "Arnd Bergmann" To: "Zhou Wang" , "Catalin Marinas" , "Will Deacon" , "Marc Zyngier" , "Oliver Upton" , "Joey Gouly" , "Suzuki K Poulose" , "Zenghui Yu" Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, "Yicong Yang" , prime.zeng@hisilicon.com, xuwei5@huawei.com Message-Id: <084ff83c-8bb7-45ea-9ae3-1d17be913c09@app.fastmail.com> In-Reply-To: <20251107072127.448953-1-wangzhou1@hisilicon.com> References: <20251107072127.448953-1-wangzhou1@hisilicon.com> Subject: Re: [PATCH v7 0/7] Add support for FEAT_{LS64, LS64_V} and related tests Content-Type: text/plain Content-Transfer-Encoding: 7bit On Fri, Nov 7, 2025, at 08:21, Zhou Wang wrote: > Armv8.7 introduces single-copy atomic 64-byte loads and stores > instructions and its variants named under FEAT_{LS64, LS64_V}. > Add support for Armv8.7 FEAT_{LS64, LS64_V}: > - Add identifying and enabling in the cpufeature list > - Expose the support of these features to userspace through HWCAP3 and cpuinfo > - Add related hwcap test > - Handle the trap of unsupported memory (normal/uncacheable) access in a VM > > A real scenario for this feature is that the userspace driver can make use of > this to implement direct WQE (workqueue entry) - a mechanism to fill WQE > directly into the hardware. > > Picked Marc's 2 patches form [1] for handling the LS64 trap in a VM on emulated > MMIO and the introduce of KVM_EXIT_ARM_LDST64B. This all looks good to me now, no further comments from my side, and I hope we can get this into the next kernel. Thanks a lot for taking care of this! Acked-by: Arnd Bergmann