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Fri, 14 Nov 2025 04:37:31 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: ALjut8WcExBk Date: Fri, 14 Nov 2025 10:37:09 +0100 From: "Arnd Bergmann" To: "Zhou Wang" , "Marc Zyngier" Cc: "Catalin Marinas" , "Will Deacon" , "Oliver Upton" , "Joey Gouly" , "Suzuki K Poulose" , "Zenghui Yu" , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, "Yicong Yang" , prime.zeng@hisilicon.com, xuwei5@huawei.com Message-Id: <113db0fb-d879-49d7-a5f2-7755558f29dd@app.fastmail.com> In-Reply-To: <1ed610f5-3f0b-614d-5e7f-2c643238bec3@hisilicon.com> References: <20251107072127.448953-1-wangzhou1@hisilicon.com> <20251107072127.448953-6-wangzhou1@hisilicon.com> <861pm4vn02.wl-maz@kernel.org> <1ed610f5-3f0b-614d-5e7f-2c643238bec3@hisilicon.com> Subject: Re: [PATCH v7 5/7] arm64: Add support for FEAT_{LS64, LS64_V} Content-Type: text/plain Content-Transfer-Encoding: 7bit On Fri, Nov 14, 2025, at 10:25, Zhou Wang wrote: > On 2025/11/14 0:26, Arnd Bergmann wrote: >> >> Are you using a particular device, or are you trying to enable >> the support in general? If you have a specific device you are >> working on, does it use the PASID data or not? > > Many thanks for your careful explanation! I got the pointer here. > > We have a real device in our SoC, which supports LS64B/ST64B/ST64BV. > For ST64BV, Our device just receives 64B data atomically, not interpret > it with PASID data. Ok, I see. So I assume this is either a kind of dedicated work queue where the IOMMU PASID is set up in advance for the user MMIO area, or it is a device that does not do any DMA at all, correct? In this case, would the device also work correctly with ST64BV0 if the ACCDATA register is fixed to a value of zero and you can only use the upper 480 bits? Would it also work if there is an unpredictable value in ACCDATA that may match the PASID of another device used by the same process? Arnd