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Fri, 24 May 2024 17:18:29 +0000 (GMT) Message-ID: <14cdedc0c6aa62d1c5aa4b770abd5bdc0f63f7c8.camel@linux.ibm.com> Subject: Re: [PATCH 1/3] KVM: arm64: Fix AArch32 register narrowing on userspace write From: Nina Schoetterl-Glausch To: Marc Zyngier , kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , stable@vger.kernel.org Date: Fri, 24 May 2024 19:18:28 +0200 In-Reply-To: <20240524141956.1450304-2-maz@kernel.org> References: <20240524141956.1450304-1-maz@kernel.org> <20240524141956.1450304-2-maz@kernel.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.1 (3.52.1-1.fc40) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 2zcVaPdxn_Gis_kAKQatAaMZImXhGwRz X-Proofpoint-ORIG-GUID: 2zcVaPdxn_Gis_kAKQatAaMZImXhGwRz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-05-24_05,2024-05-24_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 adultscore=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 clxscore=1011 bulkscore=0 mlxlogscore=936 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405240122 On Fri, 2024-05-24 at 15:19 +0100, Marc Zyngier wrote: > When userspace writes to once of the core registers, we make > sure to narrow the corresponding GPRs if PSTATE indicates > an AArch32 context. >=20 > The code tries to check whether the context is EL0 or EL1 so > that it narrows the correct registers. But it does so by checking > the full PSTATE instead of PSTATE.M. >=20 > As a consequence, and if we are restoring an AArch32 EL0 context > in a 64bit guest, and that PSTATE has *any* bit set outside of > PSTATE.M, we narrow *all* registers instead of only the first 15, > destroying the 64bit state. >=20 > Obviously, this is not something the guest is likely to enjoy. >=20 > Correctly masking PSTATE to only evaluate PSTATE.M fixes it. >=20 > Fixes: 90c1f934ed71 ("KVM: arm64: Get rid of the AArch32 register mapping= code") > Reported-by: Nina Schoetterl-Glausch > Signed-off-by: Marc Zyngier > Cc: stable@vger.kernel.org > --- > arch/arm64/kvm/guest.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c > index e2f762d959bb..d9617b11f7a8 100644 > --- a/arch/arm64/kvm/guest.c > +++ b/arch/arm64/kvm/guest.c > @@ -276,7 +276,7 @@ static int set_core_reg(struct kvm_vcpu *vcpu, const = struct kvm_one_reg *reg) > if (*vcpu_cpsr(vcpu) & PSR_MODE32_BIT) { > int i, nr_reg; > =20 > - switch (*vcpu_cpsr(vcpu)) { > + switch (*vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK) { > /* > * Either we are dealing with user mode, and only the > * first 15 registers (+ PC) must be narrowed to 32bit. Reviewed-by: Nina Schoetterl-Glausch