Re: [RESEND PATCH v4 2/2] arm64: Add software workaround for Falkor erratum 1041

Shanker Donthineni
2017-12-11T22:26:04Z

Thanks Mark, I'll post v5 patch without alternatives.

On 12/11/2017 04:45 AM, Mark Rutland wrote:
> Hi,
>
> On Sun, Dec 10, 2017 at 08:03:43PM -0600, Shanker Donthineni wrote:
>> +/**
>> + * Errata workaround prior to disable MMU. Insert an ISB immediately prior
>> + * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0.
>> + */
>> + .macro pre_disable_mmu_workaround
>> +#ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1041
>> +alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1041
>> + isb
>> +alternative_else_nop_endif
>> +#endif
>> + .endm
>
> There's really no need for this to be an alternative. It makes the
> kernel larger and more complex due to all the altinstr data and probing
> code.
>
> As Will suggested last time [1], please just use the ifdef, and always
> compile-in the extra ISB if CONFIG_QCOM_FALKOR_ERRATUM_E1041 is
> selected. Get rid of the alternatives and probing code.
>
> All you need here is:
>
> /*
> * Some Falkor parts make errant speculative instruction fetches
> * when SCTLR_ELx.M is cleared. An ISB before the write to
> * SCTLR_ELx prevents this.
> */
> .macro pre_disable_mmu_workaround
> #ifdef
> isb
> #endif
> .endm
>
>> +
>> + .macro pre_disable_mmu_early_workaround
>> +#ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1041
>> + isb
>> +#endif
>> + .endm
>> +
>
> ... and we don't need a special early variant.
>
> Thanks,
> Mark.
>
> [1] https://lkml.kernel.org/r/20171201112457.GE18083-5wv7dgnIgG8@public.gmane.org
>
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--
Shanker Donthineni
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.