From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1647BCA9EBB for ; Thu, 24 Oct 2019 16:10:52 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id C6C56205F4 for ; Thu, 24 Oct 2019 16:10:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C6C56205F4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvmarm-bounces@lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 6B58B4A5D5; Thu, 24 Oct 2019 12:10:51 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id zYvB8kyQu3-2; Thu, 24 Oct 2019 12:10:50 -0400 (EDT) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 550684A609; Thu, 24 Oct 2019 12:10:50 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 0479F4A609 for ; Thu, 24 Oct 2019 12:10:49 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 6nv-j1ghPc4n for ; Thu, 24 Oct 2019 12:10:47 -0400 (EDT) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 6A46D4A586 for ; Thu, 24 Oct 2019 12:10:47 -0400 (EDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2834228; Thu, 24 Oct 2019 09:10:47 -0700 (PDT) Received: from [10.1.196.105] (eglon.cambridge.arm.com [10.1.196.105]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 09B8D3F71F; Thu, 24 Oct 2019 09:10:45 -0700 (PDT) Subject: Re: [PATCH v2 4/5] arm64: KVM: Prevent speculative S1 PTW when restoring vcpu context To: Marc Zyngier References: <20191019095521.31722-1-maz@kernel.org> <20191019095521.31722-5-maz@kernel.org> From: James Morse Message-ID: <151fc868-6709-3017-e34d-649ec0e1812c@arm.com> Date: Thu, 24 Oct 2019 17:10:44 +0100 User-Agent: Mozilla/5.0 (X11; Linux aarch64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <20191019095521.31722-5-maz@kernel.org> Content-Language: en-GB Cc: kvm@vger.kernel.org, Catalin Marinas , Will Deacon , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu Hi Marc, On 19/10/2019 10:55, Marc Zyngier wrote: > When handling erratum 1319367, we must ensure that the page table > walker cannot parse the S1 page tables while the guest is in an > inconsistent state. This is done as follows: > > On guest entry: > - TCR_EL1.EPD{0,1} are set, ensuring that no PTW can occur > - all system registers are restored, except for TCR_EL1 and SCTLR_EL1 > - stage-2 is restored > - SCTLR_EL1 and TCR_EL1 are restored > > On guest exit: > - SCTLR_EL1.M and TCR_EL1.EPD{0,1} are set, ensuring that no PTW can occur > - stage-2 is disabled > - All host system registers are restored Reviewed-by: James Morse (whitespace nit below) > diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c > index 69e10b29cbd0..5765b17c38c7 100644 > --- a/arch/arm64/kvm/hyp/switch.c > +++ b/arch/arm64/kvm/hyp/switch.c > @@ -118,6 +118,20 @@ static void __hyp_text __activate_traps_nvhe(struct kvm_vcpu *vcpu) > } > > write_sysreg(val, cptr_el2); > + > + if (cpus_have_const_cap(ARM64_WORKAROUND_1319367)) { > + struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt; > + > + isb(); > + /* > + * At this stage, and thanks to the above isb(), S2 is > + * configured and enabled. We can now restore the guest's S1 > + * configuration: SCTLR, and only then TCR. > + */ (note for my future self: because the guest may have had M=0 and rubbish in the TTBRs) > + write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], SYS_SCTLR); > + isb(); > + write_sysreg_el1(ctxt->sys_regs[TCR_EL1], SYS_TCR); > + } > } > > diff --git a/arch/arm64/kvm/hyp/sysreg-sr.c b/arch/arm64/kvm/hyp/sysreg-sr.c > index 7ddbc849b580..fb97547bfa79 100644 > --- a/arch/arm64/kvm/hyp/sysreg-sr.c > +++ b/arch/arm64/kvm/hyp/sysreg-sr.c > @@ -117,12 +117,26 @@ static void __hyp_text __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt) > { > write_sysreg(ctxt->sys_regs[MPIDR_EL1], vmpidr_el2); > write_sysreg(ctxt->sys_regs[CSSELR_EL1], csselr_el1); > - write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], SYS_SCTLR); > + > + if (!cpus_have_const_cap(ARM64_WORKAROUND_1319367)) { > + write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], SYS_SCTLR); > + write_sysreg_el1(ctxt->sys_regs[TCR_EL1], SYS_TCR); > + } else if (!ctxt->__hyp_running_vcpu) { > + /* > + * Must only be done for guest registers, hence the context > + * test. We'recoming from the host, so SCTLR.M is already (Nit: We'recoming?) > + * set. Pairs with __activate_traps_nvhe(). > + */ > + write_sysreg_el1((ctxt->sys_regs[TCR_EL1] | > + TCR_EPD1_MASK | TCR_EPD0_MASK), > + SYS_TCR); > + isb(); > + } Thanks, James _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm